EPM9560RC304-15F vs EPM9560RC304-15C Vergleich
Detaillierter Direktvergleich von EPM9560RC304-15F von Altera und EPM9560RC304-15C von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EPM9560RC304-15F - 560-Macrocell MAX 9000 CPLD, 5V, RQFP-304 | Intel
EPM9560RC304-15F ObsoleteAltera
EPM9560RC304-15C - 560 Macro Cell MAX 9000 CPLD 117.6MHz 5V | Altera
EPM9560RC304-15C ObsoleteSpezifikationsvergleich
| Parameter | EPM9560RC304-15F | EPM9560RC304-15C |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $18,75 | $24,50 |
| Device Family | MAX 9000 | — |
| Series | EPM9560 | — |
| Macrocells | 560 | — |
| Usable Gates | 12,000 | 12,000 |
| Propagation Delay (tpd) | 16.6 ns (max) | — |
| Maximum Internal Frequency | 117.6 MHz | — |
| Core Supply Voltage | 5.0 V | — |
| User I/O Pins | 212 | — |
| Dedicated Inputs | 4 | — |
| Logic Array Blocks (LABs) | 16 (40 macrocells each) | 16 |
| Gehäuse | RQFP-304 (304-pin Plastic QFP) | 304-pin RQFP |
| Programming Technology | 5.0 V in-system EEPROM via JTAG (IEEE 1149.1) | — |
| Architecture | Multiple Array MatriX (MAX) with PIA interconnect | Multiple Array MatriX (MAX), 3rd generation |
| Boundary Scan Test (BST) | Yes, JTAG-compliant | — |
| Betriebstemperatur | -40C to +85C (industrial) | 0 C to +70 C (Commercial) |
| Process Technology | High-performance CMOS, EEPROM-based | CMOS EEPROM |
| Montageart | Surface Mount | Surface Mount |
| MSL-Level | 3 (168 hours) | — |
| RoHS-Status | [DATA_NEEDED: rohs status - not stated in source] | [DATA_NEEDED: RoHS status] |
| Family | — | MAX 9000 |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Macro Cells | — | 560 |
| User I/O Pins (maximum) | — | 212 |
| Maximum Operating Frequency | — | 117.6 MHz |
| Pin-to-Pin Propagation Delay (tPD) | — | 15 ns |
| Versorgungsspannung | — | 5.0 V |
| In-System Programmability | — | Yes (IEEE 1149.1 JTAG) |
| Program/Erase Endurance | — | 100 cycles minimum |