EPM9560RC304-15F vs EPM9560RC304-15C 比較
詳細な並列比較: EPM9560RC304-15F メーカー: Altera および EPM9560RC304-15C メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
Altera
EPM9560RC304-15F - 560-Macrocell MAX 9000 CPLD, 5V, RQFP-304 | Intel
EPM9560RC304-15F ObsoleteAltera
EPM9560RC304-15C - 560 Macro Cell MAX 9000 CPLD 117.6MHz 5V | Altera
EPM9560RC304-15C Obsolete仕様比較
| パラメータ | EPM9560RC304-15F | EPM9560RC304-15C |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $18.75 | $24.50 |
| Device Family | MAX 9000 | — |
| Series | EPM9560 | — |
| Macrocells | 560 | — |
| Usable Gates | 12,000 | 12,000 |
| Propagation Delay (tpd) | 16.6 ns (max) | — |
| Maximum Internal Frequency | 117.6 MHz | — |
| Core Supply Voltage | 5.0 V | — |
| User I/O Pins | 212 | — |
| Dedicated Inputs | 4 | — |
| Logic Array Blocks (LABs) | 16 (40 macrocells each) | 16 |
| パッケージ | RQFP-304 (304-pin Plastic QFP) | 304-pin RQFP |
| Programming Technology | 5.0 V in-system EEPROM via JTAG (IEEE 1149.1) | — |
| Architecture | Multiple Array MatriX (MAX) with PIA interconnect | Multiple Array MatriX (MAX), 3rd generation |
| Boundary Scan Test (BST) | Yes, JTAG-compliant | — |
| 動作温度 | -40C to +85C (industrial) | 0 C to +70 C (Commercial) |
| Process Technology | High-performance CMOS, EEPROM-based | CMOS EEPROM |
| 実装タイプ | Surface Mount | Surface Mount |
| MSLレベル | 3 (168 hours) | — |
| RoHS ステータス | [DATA_NEEDED: rohs status - not stated in source] | [DATA_NEEDED: RoHS status] |
| Family | — | MAX 9000 |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Macro Cells | — | 560 |
| User I/O Pins (maximum) | — | 212 |
| Maximum Operating Frequency | — | 117.6 MHz |
| Pin-to-Pin Propagation Delay (tPD) | — | 15 ns |
| 電源電圧 | — | 5.0 V |
| In-System Programmability | — | Yes (IEEE 1149.1 JTAG) |
| Program/Erase Endurance | — | 100 cycles minimum |