M7AFS600-FGG484I vs AFS600-2FGG484 Vergleich
Detaillierter Direktvergleich von M7AFS600-FGG484I von Microchip Technology und AFS600-2FGG484 von Microchip Technology. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Microchip Technology
M7AFS600-FGG484I - Fusion FPGA 600K Gates 484-BGA | Microchip
M7AFS600-FGG484I ✓ AktivMicrochip Technology
AFS600-2FGG484 - 600K Gate Mixed-Signal FPGA | Microchip
AFS600-2FGG484 ✓ AktivSpezifikationsvergleich
| Parameter | M7AFS600-FGG484I | AFS600-2FGG484 |
|---|---|---|
| Marke | Microchip Technology | Microchip Technology |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Aktiv | Aktiv |
| Programmable Logic Family | Fusion (Microsemi/Actel, now Microchip) | — |
| System Gates | 600000 gates | 600,000 gates |
| Embedded Processor | ARM CoreMP7 (ARM7TDMI-compatible) | — |
| User I/O | 172 I/O | — |
| Configuration Technology | Flash-based, on-chip | — |
| Core Supply Voltage | 1.5 V | — |
| Gehäuse | 484-BGA (FGG484), 1.0 mm ball pitch | — |
| Montageart | Surface Mount | Surface mount |
| Betriebstemperatur | -40C to +100C (industrial, I grade) | 0 °C to +85 °C |
| Memory - Listable Resource | 110592 (per DigiKey listing) | — |
| Maximum Operating Frequency | [DATA_NEEDED: maximum operating frequency] | — |
| I/O Bank Count | [DATA_NEEDED: I/O bank count] | — |
| Embedded Flash Blocks | [DATA_NEEDED: embedded flash block count] | — |
| Analog Peripherals | [DATA_NEEDED: analog peripheral configuration] | — |
| MSL-Level | [DATA_NEEDED: moisture sensitivity level] | — |
| RoHS-Status | [DATA_NEEDED: RoHS status] | — |
| Programming Tool Chain | Microchip Libero SoC (formerly Actel Libero) | — |
| Device Type | — | Fusion mixed-signal field-programmable gate array (FPGA) |
| Logic Elements | — | 110,592 logic elements |
| User I/O Count | — | 172 I/O |
| Maximum Frequency | — | 1470.59 MHz |
| Versorgungsspannung | — | 1.5 V |
| Process Technology | — | 130 nm CMOS |
| Metal Layers | — | 7 layers |
| Package Type | — | 484-pin FBGA |
| Package Body Size | — | 23 x 23 mm |
| Package Pitch | — | 1.0 mm |
| Programmable Logic | — | Flash-based programmable logic |
| Analog Capability | — | Configurable embedded analog blocks |
| Clock Management | — | Comprehensive clock generation and management circuitry |
| Configuration Memory | — | Large embedded flash-memory blocks |
| Packaging Type | — | Tray |
| RoHS Compliance | — | [DATA_NEEDED: RoHS compliance] |
| REACH Compliance | — | [DATA_NEEDED: REACH compliance] |
| AEC-Q100 Qualification | — | [DATA_NEEDED: AEC-Q100 qualification] |