MSC8157ETVT1000A vs MSC8156ESAG1000B Vergleich
Detaillierter Direktvergleich von MSC8157ETVT1000A von NXP Semiconductors und MSC8156ESAG1000B von NXP Semiconductors. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
NXP Semiconductors
MSC8157ETVT1000A - 1GHz Six-Core StarCore DSP, 783-FCBGA | NXP
MSC8157ETVT1000A ObsoleteNXP Semiconductors
MSC8156ESAG1000B - 6x SC3850 1GHz DSP SoC | NXP Semiconductors
MSC8156ESAG1000B ✗ AbgekündigtSpezifikationsvergleich
| Parameter | MSC8157ETVT1000A | MSC8156ESAG1000B |
|---|---|---|
| Marke | NXP Semiconductors | NXP Semiconductors |
| Kategorie | DSP | DSP |
| Lebenszyklusstatus | Obsolete | Ende des Lebenszyklus |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $190,89 | $112,00 |
| Manufacturer | NXP Semiconductors (formerly Freescale Semiconductor) | — |
| Series | StarCore | — |
| Type | SC3850 Six-Core Digital Signal Processor (DSP) | — |
| Architecture | StarCore SC3850, six independent cores | — |
| Core Count | 6 | — |
| Clock Rate | 1 GHz (1000 MHz) | — |
| Datenbusbreite | 64-bit | — |
| On-Chip RAM | 6.375 MB | — |
| On-Chip ROM | 96 kB | — |
| L1 Instruction Cache (per core) | 32 KB | — |
| L1 Data Cache (per core) | 32 KB | — |
| Voltage - Core | 1.0 V | — |
| Voltage - I/O | 1.0 V / 1.5 V / 2.5 V (selectable) | — |
| Interfaces | Ethernet, I²C, SPI, UART/USART, PCI, RGMII, SGMII, Serial RapidIO | — |
| Betriebstemperatur | -40°C to +105°C (Extended) | 0C to +105C |
| Gehäuse | 783-FCBGA (Flip-Chip BGA), 29 mm × 29 mm | 783-ball FCBGA (29x29 mm) |
| Pin-Anzahl | 783 | — |
| Montageart | Surface Mount (FCBGA) | Surface Mount (BGA) |
| Lead Status | Lead Free | — |
| Process Technology | CMOS | 45 nm CMOS |
| DSP Cores | — | 6x SC3850 StarCore cores |
| Core Clock Frequency | — | 1 GHz per core |
| Aggregate Performance | — | [DATA_NEEDED: aggregate MMACS rating] |
| Hardware Accelerator | — | MAPLE-B baseband accelerator (turbo decode) |
| Memory Controller | — | 64-bit DDR2/DDR3, up to 800 MT/s |
| SerDes Lanes | — | 2 lanes, SRIO or PCIe (selectable) |
| Ethernet | — | 1x Gigabit Ethernet MAC |
| Packet Engine | — | QUICC Engine subsystem |
| Security Engine | — | SEC 4.0 (Cryptographic accelerator) |
| Versorgungsspannung | — | [DATA_NEEDED: core and I/O rail voltages] |
| RoHS-Status | — | [DATA_NEEDED: RoHS compliance] |
| Lebenszyklusstatus | — | End of Life (per NXP PCN) |