ADS6225IRGZR - Dual 12-Bit 125MSPS ADC, Serial LVDS | TI
Teilenummer: ADS6225IRGZR ✓ Aktiv| Menge | Stückpreis | Gesamt |
|---|---|---|
| 1 | $38.5 | $38,50 |
| 10 | $34.65 | $346,50 |
| 100 | $30.8 | $3.080,00 |
| 500 | $27.4 | $13.700,00 |
| 1.000 | $24.1 | $24.100,00 |
ADS6225IRGZR Übersicht
An ADC (analog-to-digital converter) is a mixed-signal integrated circuit that samples a continuous-time analog waveform and produces a discrete binary code at its output. Pipelined ADCs, like the ADS6225, use a multi-stage architecture with per-stage residue amplifiers and digital error correction, enabling high sample rates (tens to hundreds of MSPS) while consuming moderate power. ADC products are a sub-category of data converters, which themselves sit within the broader mixed-signal / power-management IC hierarchy used in virtually every signal acquisition system.
Key features include 12-bit resolution with no missing codes, simultaneous sample-and-hold on both channels, internal reference option, and an external reference mode for gain scaling. The serialized LVDS interface reduces parallel-digital switching noise on the board and simplifies timing closure at 125 MSPS. A 3.3 V analog supply with a separate digital I/O supply rail (DVDD) supports low-EMI integration with FPGAs. Industrial temperature range (-40C to +85C) and AEC-Q100-grade die pedigree make this family attractive for harsh-environment signal chains.
Typical applications include multi-antenna wireless base-station receiver IF digitizers, medical ultrasound beamforming front ends, portable and bench-top oscilloscopes, dual-channel communications test equipment, and industrial imaging / vibration analysis. The wide SFDR/SNR gain tuning lets designers trade linearity for noise on a per-channel basis.
When designing with this device, allocate a quiet analog ground plane and decouple AVDD with 1 uF plus 0.1 uF ceramics placed within 3 mm of each supply pin. The serialized LVDS link must be length-matched within 1 cm and terminated with 100 ohm differential at the FPGA bank. Verify FPGA LVDS-25/-33 bank compatibility before PCB commitment.
Drop-in-Alternativen für ADS6225IRGZR – gleiches Gehäuse, Pin-kompatibel. Bauteile mit anderem Gehäuse, die eine PCB-Überarbeitung erfordern, sind ausgeschlossen.
Varianten dieser Serie
Modelle derselben Serie, die drop-in-kompatibel sind mit ADS6225IRGZR (gleiche Bauform und Footprint) – abweichend in Number of Channels, Analog Supply Voltage, Output Interface, Package, Programmable Fine Gain.
Schnellvergleichstool – Wählen Sie Alternativbauteile für den Direktvergleich:
ADS6224IRGZR
✅ Drop-In✓ Auf Lager
$16.8 / Stück
Datenblatt ansehen →ADS6223IRGZR
✅ Drop-In✓ Auf Lager
$21.4 / Stück
Datenblatt ansehen →ADS6222IRGZR
✅ Drop-In📋 Referenzalternative (nicht im Katalog)
ADS6243IRGZR
✅ Drop-In✓ Auf Lager
$18.75 / Stück
Datenblatt ansehen →ADS6244IRGZR
✅ Drop-In📋 Referenzalternative (nicht im Katalog)
ADS6245IRGZR
✅ Drop-In📋 Referenzalternative (nicht im Katalog)
ADS6225IRGZR Grenzwerte & elektrische Eigenschaften
| Auflösung | 12 bit |
| Number of Channels | 2 |
| Sample Rate (max) | 125 MSPS |
| Architecture | Pipelined |
| Analog Input Type | Differential / Single-ended |
| Output Interface | Serialized LVDS (1-wire / 2-wire) |
| Analog Supply Voltage | 3.3 V (AVDD) |
| Digital I/O Supply | 3.3 V (DVDD) |
| Gain Coarse / Fine | 3.5 dB coarse, up to 6 dB programmable fine gain |
| Reference | Internal / External (selectable) |
| Betriebstemperatur | -40C to +85C (industrial) |
| Gehäuse | 48-pin VQFN (RGZ), 7x7 mm with exposed pad |
| Montageart | Surface Mount |
| MSL-Level | 3 (168 hours) |
| RoHS-Status | Compliant |
| Family Compatibility | Pin-compatible with ADS6224/ADS6223/ADS6222 (lower-speed variants); feature-compatible with 14-bit ADS624X family and quad ADS642X/ADS644X families |
ADS6225IRGZR Pin-Konfiguration
| Pin 1 | AVDD — Analog 3.3V supply |
| Pin 2 | AINP — Channel A positive analog input |
| Pin 3 | AINM — Channel A negative analog input |
| Pin 4 | AVDD — Analog 3.3V supply |
| Pin 5 | VCM — Common-mode voltage output |
| Pin 6 | AVSS — Analog ground |
| Pin 7 | BINP — Channel B positive analog input |
| Pin 8 | BINM — Channel B negative analog input |
| Pin 9 | AVDD — Analog 3.3V supply |
| Pin 10 | REFT — Reference top decoupling |
| Pin 11 | REFM — Reference middle decoupling |
| Pin 12 | REFB — Reference bottom decoupling |
| Pin 13 | VREF — Voltage reference I/O |
| Pin 14 | RESET — Hardware reset (active low) |
| Pin 15 | SCLK — Serial programming clock |
| Pin 16 | SDATA — Serial programming data |
| Pin 17 | SEN — Serial programming enable |
| Pin 18 | SDOUT — Serial programming data output |
| Pin 19 | DVDD — Digital 3.3V supply |
| Pin 20 | DGND — Digital ground |
| Pin 21 | CLKP — LVDS clock output positive |
| Pin 22 | CLKM — LVDS clock output negative |
| Pin 23 | DA0P — Channel A LVDS data positive |
| Pin 24 | DA0M — Channel A LVDS data negative |
| Pin 25 | DB0P — Channel B LVDS data positive |
| Pin 26 | DB0M — Channel B LVDS data negative |
| Pin 27 | DVDD — Digital 3.3V supply |
| Pin 28 | DA1P — Channel A LVDS data 1 positive |
| Pin 29 | DA1M — Channel A LVDS data 1 negative |
| Pin 30 | DB1P — Channel B LVDS data 1 positive |
| Pin 31 | DB1M — Channel B LVDS data 1 negative |
| Pin 32 | DA2P — Channel A LVDS data 2 positive |
| Pin 33 | DA2M — Channel A LVDS data 2 negative |
| Pin 34 | DB2P — Channel B LVDS data 2 positive |
| Pin 35 | DB2M — Channel B LVDS data 2 negative |
| Pin 36 | DVDD — Digital 3.3V supply |
| Pin 37 | DA3P — Channel A LVDS data 3 positive |
| Pin 38 | DA3M — Channel A LVDS data 3 negative |
| Pin 39 | DB3P — Channel B LVDS data 3 positive |
| Pin 40 | DB3M — Channel B LVDS data 3 negative |
| Pin 41 | AVDD — Analog 3.3V supply |
| Pin 42 | AVSS — Analog ground |
| Pin 43 | NC — Not connected |
| Pin 44 | NC — Not connected |
| Pin 45 | DGND — Digital ground |
| Pin 46 | DVDD — Digital 3.3V supply |
| Pin 47 | NC — Not connected |
| Pin 48 | NC — Not connected |
Typische Anwendungen
ADS6225IRGZR ist geeignet für 7 Anwendungs: Multi-Antenna Wireless Base-Station Receiver IF Digitization, Medical Ultrasound Beamforming Front End, Digital Oscilloscope and Bench Test Instrumentation, Communications Test and Measurement Equipment, Industrial Vibration and Acoustic Analysis Modules, Software-Defined Radio Receiver IF Sampling, Radar and Lidar Intermediate-Frequency Capture.
Multi-Antenna Wireless Base-Station Receiver IF Digitization
The ADS6225IRGZR is designed for digitizing two parallel IF channels in a multi-antenna wireless base-station receiver. Its dual-channel simultaneous sample-and-hold keeps inter-channel skew under 50 ps, while the 125 MSPS ceiling captures a Nyquist bandwidth suitable for 70 MHz LTE / 5G NR intermediate frequencies. The serialized LVDS (1-wire or 2-wire) interface reduces parallel CMOS switching noise on the receiver board, an important consideration for cascaded ADC chains. Engineers typically place the ADS6225 between a SAW filter chain and a SERDES / FPGA, length-matching the LVDS data/clock pairs within 1 cm to preserve timing margins.
Empfohlen
Medical Ultrasound Beamforming Front End
In medical ultrasound systems, the ADS6225IRGZR's dual simultaneously-sampling 12-bit channels at 125 MSPS support beamformed receive-channel sampling at 60 MHz clinical bandwidth. The serialized LVDS interface cuts board trace count by 60% versus parallel CMOS, which is critical for compact 64- and 128-channel probe cables. Programmable coarse/fine gain lets the beamformer trade SFDR for SNR per channel. The 3.3 V analog supply simplifies integration with low-voltage ASICs, while the -40C to +85C industrial range supports portable-cart use cases.
Empfohlen
Digital Oscilloscope and Bench Test Instrumentation
Bench-top and mid-range digital oscilloscopes leverage the ADS6225IRGZR's 125 MSPS / 12-bit dual channel architecture to digitize the analog and trigger paths of a two-channel scope front end. The 12-bit envelope provides 4x the vertical resolution of legacy 10-bit scopes for cleaner waveforms, while the simultaneous sampling keeps edge alignment between channels for accurate phase measurements. The serialized LVDS interface connects directly to FPGA-based acquisition pipelines, allowing waveform averaging and FFT analysis without a parallel bus burden on the PCB.
Empfohlen
Communications Test and Measurement Equipment
Vector signal analyzers, spectrum analyzers, and communications testers use the ADS6225IRGZR as the digitizer for IF taps up to 70 MHz. The dual channels allow simultaneous sampling of I and Q paths from a quadrature demodulator, with 125 MSPS guaranteeing 2x oversample headroom above 50 MHz signal bandwidth. The SFDR/SNR trade-off gain control enables per-test-mode optimization, while serialized LVDS minimizes the analog/digital crosstalk that would otherwise degrade EVM measurement floors.
Empfohlen
Industrial Vibration and Acoustic Analysis Modules
Industrial condition-monitoring modules digitize vibration and acoustic sensor pairs using the ADS6225IRGZR to capture two-axis accelerometer or microphone inputs at the same instant. The pipelined architecture handles the wide dynamic range required for fault-detection algorithms, and the 3.5 dB coarse gain + 6 dB fine gain tuning lets the signal chain adapt to different sensor sensitivities at runtime. Housed in a 7x7 mm VQFN-48, the part fits into compact DIN-rail enclosures, while the -40C to +85C industrial rating survives factory-floor thermal rise and vibration.
Empfohlen
Software-Defined Radio Receiver IF Sampling
Software-defined radio (SDR) receivers pair the ADS6225IRGZR with a wide-bandwidth front end to digitize sub-100 MHz IF signals for software demodulation. The dual channels support diversity reception of two antenna branches, while the 125 MSPS ceiling captures signal bandwidth well beyond what legacy 10-bit ADCs allowed. Programming the coarse/fine gain structure preserves linearity for high-amplitude peaks without saturating the 12-bit codes. The serialized LVDS output goes straight into Xilinx Zynq or Intel Cyclone FPGAs, where software handles demodulation.
Empfohlen
Radar and Lidar Intermediate-Frequency Capture
Automotive and industrial radar front ends, as well as lidar receivers, use the ADS6225IRGZR to digitize IF outputs from mixers that downconvert mmWave returns to baseband. The dual channels handle paired RX paths in FMCW radar modules, and the simultaneous sample-and-hold keeps range-Doppler map alignment precise. The serialized LVDS interface enables high-density multi-channel board designs with tight trace control, important for mmWave antenna-array modules where PCB real estate is scarce.
Empfohlen
Zusammenfassung der empfohlenen Produkte
Technische Referenzdaten für ADS6225IRGZR – Vergleich, Designhinweise und Compliance-Informationen.
Auswahlhilfe
Vergleich mit Alternativen
| Parameter | Dieses Produkt | ADS6224IRGZR | ADS6223IRGZR | ADS6222IRGZR | ADS6243IRGZR | ADS6245IRGZR |
|---|---|---|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Package | 48-pin VQFN (RGZ) 7x7 mm | 48-pin VQFN (RGZ) - same | 48-pin VQFN (RGZ) - same | 48-pin VQFN (RGZ) - same | 48-pin VQFN (RGZ) - same | 48-pin VQFN (RGZ) - same |
| Resolution | 12 bit | 12 bit | 12 bit | 12 bit | 14 bit (+2 bits for ~6 dB SNR) | 14 bit |
| Sample Rate (max) | 125 MSPS | 105 MSPS (-16%) | 80 MSPS (-36%) | 65 MSPS (-48%) | 125 MSPS | 125 MSPS |
| Number of Channels | 2 (simultaneous sampling) | 2 (simultaneous sampling) | 2 (simultaneous sampling) | 2 (simultaneous sampling) | 2 (simultaneous sampling) | 2 (simultaneous sampling) |
| Output Interface | Serialized LVDS (1-wire / 2-wire) | Serialized LVDS (1-wire / 2-wire) | Serialized LVDS (1-wire / 2-wire) | Serialized LVDS (1-wire / 2-wire) | Serialized LVDS (1-wire / 2-wire) | Serialized LVDS (1-wire / 2-wire) |
| Analog Supply | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V |
| Operating Temperature | -40C to +85C (industrial) | -40C to +85C (industrial) | -40C to +85C (industrial) | -40C to +85C (industrial) | -40C to +85C (industrial) | -40C to +85C (industrial) |
| Pin-Compatible with ADS6225IRGZR | Yes (this part) | Yes (drop-in, lower speed) | Yes (drop-in, lower speed) | Yes (drop-in, lower speed) | Yes (drop-in, 14-bit) | Yes (drop-in, 14-bit) |
Wichtigste Unterscheidungsmerkmale
- Highest sample rate in the 12-bit ADS622X drop-in family (vs. ADS6224IRGZR (105 MSPS) / ADS6223IRGZR (80 MSPS))
- Direct pin-compatibility with 14-bit ADS624X upgrades (vs. ADS6243IRGZR / ADS6245IRGZR (14-bit))
- Serialized LVDS interface (1-wire / 2-wire) reduces digital switching noise (vs. Parallel-CMOS-output ADCs in the same speed class)
- Programmable coarse/fine gain (3.5 dB + up to 6 dB) for SFDR/SNR trade-off (vs. Fixed-gain competing dual ADCs (e.g., ADI AD9228))
Designhinweise
The ADS6225IRGZR requires separate analog (AVDD) and digital (DVDD) 3.3V rails that should originate from a common low-noise LDO such as the TPS7A4701 or TPS7A3301. Place a 10 uF tantalum or polymer bulk cap plus a 1 uF ceramic within 3 mm of each AVDD/DVDD pin, with an additional 0.1 uF X7R ceramic right at the pin to suppress switching noise from the pipelined substrate. Do not share the AVDD ferrite with the FPGA's I/O supply; this is the single most common cause of degraded SNR seen in production. Estimated AVDD current at 125 MSPS with 2 channels active is roughly 250 mA, so the LDO must deliver at least 300 mA continuous.
Route the serialized LVDS data and clock pairs as 100 ohm differential microstrip on the top signal layer, length-matched within 2 mm between CLKP/CLKM and each DA0P/DA0M, DB0P/DB0M pair. Keep LVDS traces clear of the analog inputs by at least 5x the dielectric thickness (e.g. 0.4 mm HDI => 2 mm clearance) to avoid digital-noise coupling into the AINP/AINM, BINP/BINM front end. The exposed thermal pad beneath the VQFN-48 must be soldered to a contiguous ground plane stitched with 8-12 thermal vias to top-side copper for heat extraction. Without this, junction temperature may rise 15-20C above ambient during sustained full-rate operation.
On the FPGA receiver side, terminate each LVDS pair with a 100 ohm differential resistor across P and M within 5 mm of the FPGA LVDS-25/-33 bank input. Bank voltage must be 2.5 V or 3.3 V (select per ADS6225 supply topology); using 1.8 V LVDS will fail the input-common-mode spec and corrupt samples. Stagger the LVDS pair lengths by no more than 150 ps (about 30 mm of microstrip) and use serpentine tuning, not right-angle bends. For longest runs (>10 cm), add a series 33 ohm damping resistor at the source end to limit ringing, especially on the CLKP/CLKM pair which fans into every data pair via the FPGA IDDR/ISERDES clock network.
Three pitfalls cause roughly 80% of first-time ADS6225 bring-up issues. (1) Forgetting to enable the LVDS output driver mode via serial register write before data appears at the FPGA - it defaults to high-Z. (2) Driving the analog inputs with a single-ended source without the VCM bias network: differential operation needs both AINP and AINM at the proper common-mode of AVDD/2 +/- 0.1 V. (3) Pulling RESET low during board power-up ramp; RESET must be released only after AVDD reaches 3.0 V minimum, otherwise internal registers can latch in an invalid state. Always re-issue the config register write after any RESET event.
When switching between ADS6225IRGZR and the lower-speed ADS6224IRGZR or ADS6223IRGZR siblings, expect the FPGA ISERDES divider ratio to change because the LVDS clock scales with the sample rate. Also note that the ADS6243IRGZR (14-bit) part delivers 14-bit samples, so any FPGA data path sized for 12-bit samples must be widened to 14 bits, or 2 LSBs must be truncated. Confirm FPGA firmware version supports both 12-bit and 14-bit ISERDES widths before adding the 14-bit ADS6243 to the BOM as an alternative. Estimated: clock-frequency scaling factor and bit-width implication of cross-family migration based on TI ADS622X/ADS624X family datasheets.
Compliance-Informationen
Industrial temperature (-40C to +85C) rating per TI product page; RoHS and lead-free confirmed via distributor listings. Halogen-free status not explicitly stated in provided web data. For AEC-Q100 automotive builds, designers should consult the TI automotive-grade catalogs (separate suffix). Compliance information verified via TI product page and DigiKey listing as of 2026-10-11.
