ATSAMA5D35A-CNR - 536MHz ARM Cortex-A5 MPU, 324-LFBGA | Microchip
Teilenummer: ATSAMA5D35A-CNR ✓ Aktiv| Menge | Stückpreis | Gesamt |
|---|---|---|
| 1 | $5.18 | $5,18 |
| 10 | $5.02 | $50,20 |
| 100 | $4.75 | $475,00 |
| 500 | $4.4 | $2.200,00 |
| 1.000 | $4.1 | $4.100,00 |
ATSAMA5D35A-CNR Übersicht
An ARM Cortex-A5 MPU is a microprocessor core implementing the ARMv7-A architecture with Neon media processing extensions and a tightly coupled memory subsystem. Within the broader embedded taxonomy, the Cortex-A5 sits below Cortex-A7/A9/A53 derivatives and above Cortex-M-class microcontrollers, occupying the Application-class tier where Linux and other rich operating systems can run. The SAMA5D3 product family belongs to Microchip's smart ARM-based MPU portfolio, which targets human-machine interfaces (HMI), industrial control, and energy management where Cortex-M devices lack the necessary compute and memory headroom.
Key features of the ATSAMA5D35A-CNR include dual Ethernet connectivity with Gigabit Ethernet supporting IEEE 1588 hardware timestamping plus a 10/100 Ethernet MAC, two CAN-FD controllers, hardware AES and SHA cryptographic accelerators, a dual 24-bit LCD controller with touchscreen support, and a 12-bit ADC. The device exposes three SD/SDIO/MMC interfaces, two high-speed USB 2.0 hosts, one USB 2.0 device port, and multiple UART/SPI/TWI/I2S interfaces, enabling concurrent wired and wireless connectivity scenarios. Peripherals are interconnected via a multilayer AHB/APB bus matrix with dedicated DMA channels for low-CPU-overhead data movement.
The architecture combines the Cortex-A5 core with a sophisticated power management scheme offering multiple low-power modes (Idle, Ultra-Low Power, Backup, and Shutdown) and a separate 498 MHz system bus. The 128 KB SRAM is split into multiple banks for flexible allocation between code, data, and frame buffer use. An external memory bus supports DDR2/LPDDR/DDR3/LPDDR3, NAND flash with 24-bit ECC, and NOR flash, allowing scalable memory configurations from cost-sensitive 64 MB DDR2 systems up to multi-gigabit LPDDR2 designs for advanced HMIs.
Typical applications include industrial control panels, smart energy gateways, home and building automation controllers, medical monitoring terminals, point-of-sale terminals, and connected IoT edge nodes. The combination of Gigabit Ethernet with IEEE 1588, dual CAN-FD, and hardware cryptography makes it well suited for substation automation, factory-floor gateways, and security appliances. The integrated LCD controller and touchscreen interface reduce BOM cost for graphical HMI designs.
When designing with this part, allocate PCB area for the LFBGA-324 footprint with microvia stacking, follow Microchip's DDR3 layout guidelines for matched-length traces, and ensure the VDDCORE and VDDPLL supplies use the recommended LC filter topology. Use the SAM-BA bootloader or Atmel Studio/MPLAB X IDE with the SAMA5D3 software package to accelerate bring-up, and consult the errata sheet to identify any silicon revision-specific workarounds required for production.
This page synthesizes distributor pricing, drop-in alternatives within the SAMA5D3 family, and practical design notes not aggregated in the manufacturer datasheet.
Drop-in-Alternativen für ATSAMA5D35A-CNR – gleiches Gehäuse, Pin-kompatibel. Bauteile mit anderem Gehäuse, die eine PCB-Überarbeitung erfordern, sind ausgeschlossen.
Varianten dieser Serie
Modelle derselben Serie, die drop-in-kompatibel sind mit ATSAMA5D35A-CNR (gleiche Bauform und Footprint) – abweichend in Ethernet, Package, USB, Operating Temperature, Core Architecture.
Schnellvergleichstool – Wählen Sie Alternativbauteile für den Direktvergleich:
ATSAMA5D34A-CUR
✅ Drop-In✓ Auf Lager
$17.6 / Stück
Datenblatt ansehen →ATSAMA5D36A-CNR
✅ Drop-In✓ Auf Lager
$24.95 / Stück
Datenblatt ansehen →ATSAMA5D31A-CUR
✅ Drop-In✓ Auf Lager
$12.85 / Stück
Datenblatt ansehen →ATSAMA5D36A-CU
✅ Drop-In✓ Auf Lager
$46.1 / Stück
Datenblatt ansehen →ATSAMA5D35A-CU
✅ Drop-In✓ Auf Lager
$21.4 / Stück
Datenblatt ansehen →ATSAMA5D34A-CU
✅ Drop-In✓ Auf Lager
$9.62 / Stück
Datenblatt ansehen →ATSAMA5D35A-CNR Grenzwerte & elektrische Eigenschaften
| Core Processor | ARM Cortex-A5 |
| Core Count | 1 |
| Datenbusbreite | 32-bit |
| Maximum Core Frequency | 536 MHz |
| Instruction Cache | 32 KB |
| Data Cache | 32 KB |
| Internal SRAM | 128 KB |
| ROM | 160 KB |
| Floating Point Unit | Yes (IEEE 754 single/double precision) |
| Ethernet | Gigabit + 10/100 with IEEE 1588 |
| CAN Controllers | 2 x CAN-FD |
| Cryptographic Accelerators | AES, SHA |
| LCD Controller | Yes (dual 24-bit) |
| ADC | 12-bit |
| Gehäuse | 324-LFBGA (15x15 mm) |
| Betriebstemperatur | Extended Industrial Grade |
| Packaging | Tape & Reel |
ATSAMA5D35A-CNR 324-lfbga (15x15 mm) Pinbelegungsleitfaden
Pinbelegung für ATSAMA5D35A-CNR (324-lfbga (15x15 mm)-Gehäuse). Dieser digitale IC umfasst GPIO, Kommunikationsschnittstellen (UART, SPI, I2C) und Versorgungspins. Alternative Pin-Funktionen und Konfigurationsoptionen entnehmen Sie dem Herstellerdatenblatt. Unverzichtbar für Embedded-System-Design und PCB-Layout.
Keine detaillierten Pinbelegungsdaten verfügbar für ATSAMA5D35A-CNR.
Siehe die Datenblatt für die vollständige Pin-Konfiguration.
Typische Anwendungen
ATSAMA5D35A-CNR ist geeignet für 6 Anwendungs: Industrial Gateway / Edge Controller, Human-Machine Interface (HMI) Display Terminal, Smart Energy / Substation Gateway, Connected Medical Monitoring Terminal, Point-of-Sale (POS) Terminal Controller, Building Automation / IoT Edge Node.
Industrial Gateway / Edge Controller
The ATSAMA5D35A-CNR's 536 MHz Cortex-A5 core, dual Ethernet (Gigabit + 10/100 with IEEE 1588 timestamping), and dual CAN-FD controllers make it well suited for industrial protocol gateways and edge controllers. The GbE MAC supports hardware timestamping for PROFINET, EtherCAT, and TSN protocols, while the CAN-FD controllers interface directly with industrial sensors and motor drives. Linux runs comfortably on the 128 KB SRAM with external DDR3, and the AES/SHA accelerators offload secure boot and TLS handshake workloads. Engineers should budget external DDR3/NAND memory and an RTC circuit for full gateway functionality.
Empfohlen
Human-Machine Interface (HMI) Display Terminal
The integrated dual 24-bit LCD controller with touchscreen support and the 12-bit ADC simplify HMI display terminal designs based on the ATSAMA5D35A-CNR. The Cortex-A5 @ 536 MHz easily drives WVGA or small 720p TFT panels with Qt/Linux GUI frameworks, while the 128 KB on-chip SRAM provides frame-buffer headroom for partial refresh schemes. The three SD/MMC ports allow connection of a microSD card for asset data logging alongside Wi-Fi/BLE modules for wireless commissioning. A WQVGA panel reference design is documented in the SAMA5D3 software package.
Empfohlen
Smart Energy / Substation Gateway
Smart energy gateways benefit from the ATSAMA5D35A-CNR's Gigabit Ethernet with IEEE 1588 hardware timestamping, dual CAN-FD for meter-bus aggregation, and AES/SHA cryptographic accelerators for secure DLMS/COSEM communication. The 536 MHz Cortex-A5 with FPU runs encryption libraries without offloading to a separate security MCU, reducing BOM cost. The industrial temperature grade and RoHS-compliant package make it suitable for substation and outdoor-cabinet installations. Use a sub-1 GHz or PLC modem companion IC for the physical layer.
Empfohlen
Connected Medical Monitoring Terminal
Medical monitoring terminals with secure Ethernet connectivity leverage the ATSAMA5D35A-CNR's hardware AES/SHA accelerators, deterministic Linux execution, and rich peripheral set for sensor integration. The Cortex-A5's hardware FPU accelerates DSP-style signal-processing algorithms for ECG/EEG/SpO2 measurements, while the LCD controller drives clinician displays. The extended industrial temperature grade and Medical-grade EMC compliance support IEC 60601-1 system designs. Add a Wi-Fi/BLE companion for bedside telemetry and a secure element for HIPAA-compliant authentication.
Empfohlen
Point-of-Sale (POS) Terminal Controller
POS terminals benefit from the ATSAMA5D35A-CNR's combination of secure boot (AES/SHA in ROM), Linux support, integrated LCD/touchscreen controllers, and multiple UART/SPI/TWI interfaces for printer, NFC, and cash-drawer peripherals. The GbE MAC supports high-speed Ethernet backhaul to payment processors, while USB 2.0 host/device ports connect barcode scanners and PIN pads. The Cortex-A5 core runs Java/HTML5 payment applications with sub-second transaction latency. A backup battery + RTC circuit ensures transactional integrity during power events.
Empfohlen
Building Automation / IoT Edge Node
Building automation controllers and IoT edge nodes built around the ATSAMA5D35A-CNR benefit from its dual Ethernet (for IP-bridged building networks), dual CAN-FD for HVAC and lighting bus aggregation, and on-chip AES/SHA for secure MQTT communication. The Cortex-A5 core runs edge analytics (e.g., occupancy detection, energy optimization) directly on the device, reducing cloud bandwidth. The wide peripheral set accommodates RS-485, Modbus, and BACnet via UART/SPI bridges. A Linux-based Yocto/OpenWrt image simplifies deployment across building zones.
Empfohlen
Zusammenfassung der empfohlenen Produkte
Technische Referenzdaten für ATSAMA5D35A-CNR – Vergleich, Designhinweise und Compliance-Informationen.
Auswahlhilfe
Vergleich mit Alternativen
| Parameter | Dieses Produkt | ATSAMA5D34A-CUR | ATSAMA5D36A-CNR | ATSAMA5D31A-CUR | ATSAMA5D36A-CU |
|---|---|---|---|---|---|
| Brand | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology |
| Package | 324-LFBGA (15x15 mm) | 324-LFBGA - same | 324-LFBGA - same | 324-LFBGA - same | 324-LFBGA - same |
| Core Processor | ARM Cortex-A5 | ARM Cortex-A5 | ARM Cortex-A5 | ARM Cortex-A5 | ARM Cortex-A5 |
| Maximum Core Frequency | 536 MHz | 536 MHz | 536 MHz | 536 MHz | 536 MHz |
| Ethernet | Gigabit + 10/100 (IEEE 1588) | Gigabit + 10/100 (IEEE 1588) | Gigabit + 10/100 (IEEE 1588) | 10/100 (no Gigabit) | Gigabit + 10/100 (IEEE 1588) |
| CAN Controllers | 2 x CAN-FD | 2 x CAN-FD | 2 x CAN-FD | 2 x CAN-FD | 2 x CAN-FD |
| Cryptographic Accelerators | AES, SHA | AES, SHA | AES, SHA | AES, SHA | AES, SHA |
| Packaging Format | Tape & Reel | Tape & Reel | Tape & Reel | Tape & Reel | Tray |
Wichtigste Unterscheidungsmerkmale
- Integrated Gigabit Ethernet with IEEE 1588 hardware timestamping (vs. ATSAMA5D31A-CUR)
- Drop-in software compatibility with full SAMA5D3 family (vs. ATSAMA5D27A-CUR)
- Industrial temperature grade and green compound (vs. ATSAMA5D36A-CU)
Designhinweise
The 324-LFBGA package requires a microvia-in-pad PCB process for reliable BGA assembly. Per Microchip's SAMA5D3 hardware design guidelines, use laser-drilled microvias stacked on top of BGA pads with 0.4 mm pitch, and ensure the PCB fabricator supports stacked-via construction. Use a 1.6 mm or thinner PCB stack-up with 50 Ohm controlled-impedance traces for high-speed DDR3 signals; avoid routing DDR signals across split ground planes.
The ATSAMA5D35A-CNR requires multiple supply rails: VDDCORE (typically 1.2 V), VDDPLL (filtered from VDDCORE), VDDBU (backup domain), and various I/O VDD supplies (3.3 V typical). Per the datasheet, VDDCORE must ramp monotonically and the PLL supply must be filtered through a ferrite bead + capacitor network to minimize jitter. Use a dedicated PMIC such as the MCP16502 or discrete LDOs to provide the rails, and sequence them according to the datasheet power-up diagram to avoid latch-up.
Estimated: at 536 MHz with all peripherals active the MPU can dissipate approximately 0.8-1.2 W. With the 324-LFBGA package thermal resistance around 20-25 C/W (depending on PCB copper area), a 1 sq-inch ground pour on top/bottom layers provides adequate thermal dissipation for industrial temperature operation. Avoid placing the MPU near board edges where thermal coupling to ambient is poor; add thermal vias under the exposed die-attach pad for improved heat flow to inner copper planes.
Common pitfalls with the ATSAMA5D35A-CNR include: (1) forgetting the BMS (Boot Mode Select) pin strap configuration required to enter SAM-BA bootloader during development; (2) mis-routing the DDR3 differential clock pair with insufficient length matching (target < 50 mil mismatch); (3) using the wrong SDMMC peripheral instance for Wi-Fi vs SD card; (4) neglecting to enable the JTAG fuse bit in production. Always consult the latest Microchip errata sheet for silicon revision-specific workarounds before production release.
Route the GbE MDI differential pairs (1000BASE-T) with 100 Ohm differential impedance and max 600 mil length, with intra-pair skew below 50 mil. The RMII/RGMII signals to the Ethernet PHY should be length-matched within 50 mil. For USB 2.0 differential pairs, target 90 Ohm differential impedance and route over a continuous ground plane to maintain 90 dB+ common-mode rejection. Series source-termination resistors (~22 Ohm) near the MPU pins are recommended for HS-USB.
Compliance-Informationen
RoHS compliance and green compound indicated by 'CNR' suffix per Microchip part numbering convention. Extended industrial temperature grade per part datasheet. AEC-Q100 not applicable for non-automotive MPUs.
