ATSAMA5D36A-CU - ARM Cortex-A5 MPU 536MHz LFBGA-324 | Microchip
MPN: ATSAMA5D36A-CU ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $60.44 | $60.44 |
| 10 | $56.8 | $568.00 |
| 100 | $52.95 | $5,295.00 |
| 500 | $49.4 | $24,700.00 |
| 1,000 | $46.1 | $46,100.00 |
ATSAMA5D36A-CU Overview
A microprocessor (MPU) is a processor chip that serves as the central processing unit of an embedded system, integrating CPU core, caches, memory controller, and a wide range of peripherals on a single die. Within the broader semiconductor taxonomy, an MPU sits above microcontrollers (MCUs) in integration and performance: MPU typically runs an operating system (Linux, RTOS) from external DRAM/NAND, while MCU executes bare-metal code from internal flash. The SAMA5D3 family targets mid-range graphical and connectivity workloads where deterministic real-time response and rich peripherals are both required.
Key features of the ATSAMA5D36A-CU include a 16-bit LPDDR/DDR2/LPDDR2 controller (single rank), a hardware graphics LCD controller supporting up to 2048x2048 resolution, one Gigabit Ethernet MAC, a 10/100 Ethernet MAC, three USB 2.0 ports (two host plus one device or three host ports), two HSIC ports, three SD/SDIO/MMC controllers, and a 12-bit ADC. The device operates from a 1.08V to 1.32V core supply and 1.2V/1.8V/3.3V I/O rails, with industrial-grade -40C to +85C temperature support.
The internal architecture pairs the Cortex-A5 core with an NEON media engine absent on this variant (which is the distinguishing feature relative to NEON-equipped siblings), a multi-layer AHB/AXI bus matrix for high-throughput DMA, and dedicated hardware accelerators for crypto (AES, 3DES, SHA), image sensor interface (ISI), and capacitive touch. The 15x15 mm BGA enables compact board designs for space-constrained embedded products.
Typical applications include industrial control panels, smart energy gateways, IoT edge nodes, medical patient monitoring terminals, building automation controllers, and connected consumer appliances. The integrated gigabit Ethernet and graphics LCD controller streamline BOM and PCB area for designs that require both networked connectivity and a human-machine interface display.
When designing with the ATSAMA5D36A-CU, allocate dedicated ground and decoupling layers under the package and follow Microchip's recommended power sequencing (VDDPLL first, then VDDUTMIC, then VDDUTMI, then VDDANA) to prevent latch-up at startup. Because this part uses LPDDR/DDR2 external memory, route the 16-bit memory bus with controlled impedance and matched length to maintain signal integrity at the target SDRAM clock.
This page synthesizes Microchip datasheet specifications, current distributor pricing, available same-family drop-in alternatives, and PCB-level design guidance that goes beyond the standalone datasheet summary.
Drop-in alternatives for ATSAMA5D36A-CU — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with ATSAMA5D36A-CU (same form factor and footprint) — differing in Package, Ethernet, USB, LCD Controller, Core Architecture.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
ATSAMA5D36A-CN
✅ Drop-In✓ In Stock
$11.4 / Unit
View Datasheet →ATSAMA5D35A-CU
✅ Drop-In✓ In Stock
$21.4 / Unit
View Datasheet →ATSAMA5D34A-CU
✅ Drop-In✓ In Stock
$9.62 / Unit
View Datasheet →ATSAMA5D27A-CU
✅ Drop-In✓ In Stock
$7.83 / Unit
View Datasheet →ATSAMA5D28A-CUR
✅ Drop-In✓ In Stock
$10.8 / Unit
View Datasheet →ATSAMA5D36A-CU Maximum Ratings & Electrical Characteristics
| Core Architecture | ARM Cortex-A5 32-bit RISC |
| Maximum CPU Clock | 536 MHz |
| Instruction Cache | 32 KB |
| Data Cache | 32 KB |
| Internal SRAM | 128 KB |
| Floating Point Unit | Yes (hardware FPU) |
| NEON Media Engine | No |
| Memory Controller | 16-bit LPDDR/LPDDR2/DDR2 (single rank) |
| External Bus Interface | EBI (NOR/NAND/SRAM) |
| LCD Controller | Yes, up to 2048x2048 (hardware graphics accelerator) |
| Ethernet | 1x Gigabit MAC + 1x 10/100 MAC (GMII/RGMII/RMII/MII) |
| USB | USB 2.0 host/device x3 + HSIC x2 |
| SD/MMC/SDIO | 3 controllers |
| ADC | 12-bit, 8-channel |
| Core Supply Voltage | 1.08 V to 1.32 V |
| I/O Supply Voltages | 1.2 V, 1.8 V, 3.3 V |
| Operating Temperature | -40 C to +85 C (industrial) |
| Package | 324-ball LFBGA, 15 x 15 mm |
| Mounting Type | Surface Mount |
| RoHS Status | Compliant |
ATSAMA5D36A-CU 324-ball lfbga, 15 x 15 mm Pin Configuration Guide
Pin configuration for ATSAMA5D36A-CU (324-ball lfbga, 15 x 15 mm package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for ATSAMA5D36A-CU.
Refer to the datasheet for full pin configuration.
Typical Applications
ATSAMA5D36A-CU is suitable for 7 applications: Industrial HMI Control Panels, Smart Energy Gateways, Connected Medical Devices, Building Automation Controllers, IoT Edge Gateways, Multimedia Consumer Devices, Touch-Screen Operator Panels.
Industrial HMI Control Panels
The ATSAMA5D36A-CU is ideal for industrial human-machine interface panels thanks to its hardware 2D graphics accelerator and integrated LCD controller that drive resolutions up to 2048x2048 with dual overlays and color-space conversion. The 536 MHz Cortex-A5 core runs Linux comfortably, while the 128 KB on-chip SRAM and dedicated ISI block accelerate camera preview, fault log buffering, and responsive touch gestures. Designers place the device alongside an LPDDR2 chip and a small NOR flash, then use the 10/100 Ethernet MAC for Modbus TCP and the Gigabit MAC for OPC UA over an industrial gateway. Compared with discrete LCD controllers plus an MCU host, integrating the GPU onto the MPU removes a bridge chip and reduces BOM cost in a typical 7 to 10 inch WVGA panel.
Recommended
Smart Energy Gateways
In a smart-meter or sub-station gateway, the ATSAMA5D36A-CU provides the CPU headroom for encrypted DLMS/COSEM or IEC 61850 protocol stacks, and its AES, 3DES, and SHA hardware accelerators remove hundreds of CPU cycles per packet compared with software crypto. The DDR2/LPDDR2 controller carries protocol buffers, the Gigabit MAC backhauls data over WAN, and the CAN 1.0B interface links to meter-side sensing. Industrial -40C to +85C operation lets the same board drive outdoor-enclosure designs. Compared with a smaller Cortex-M4 gateway, the ATSAMA5D36A-CU adds TLS handshake acceleration for secure firmware updates and supports on-device graphical web UIs without an external MPU.
Recommended
Connected Medical Devices
The ATSAMA5D36A-CU fits patient-monitoring and point-of-care instrumentation where deterministic data handling and a low-noise LCD display are both critical. The 32KB + 32KB L1 caches plus 128KB SRAM keep ECG / SpO2 sample buffers in fast memory, while the integrated 12-bit ADC and ISI bridge let the same board accept analog front-end inputs and a low-cost CMOS camera. Medical-device firmware typically runs on Linux with FDA-cleared BSPs, where the MPU's AES engine protects PHI at rest. Compared with pure Cortex-M based designs, the ATSAMA5D36A-CU accelerates display rendering, supports richer HMI, and reduces the number of external peripherals on the board.
Recommended
Building Automation Controllers
For HVAC and access-control panels, the ATSAMA5D36A-CU delivers the mix of communication protocols and graphics required for modern building-management systems. The triple USB 2.0 controllers connect to Wi-Fi/Bluetooth modules, the GbE MAC carries BACnet/IP traffic, and the LCD controller drives touch panels sized 4 to 12 inches. Linux4SAM support includes BACnet stack bindings, and the 324-LFBGA package leaves room for a stacked-DDR2 / eMMC combo on a 4-layer PCB. Compared with multi-chip Cortex-M + external GPU solutions, integrating an ARM Cortex-A5 with a hardware 2D accelerator at 536 MHz simplifies the BOM and reduces firmware fragmentation across two MCUs.
Recommended
IoT Edge Gateways
The ATSAMA5D36A-CU delivers an integrated Cortex-A5 platform for industrial IoT edge nodes that aggregate sensor data, run MQTT/Sparkplug brokers, and forward to cloud brokers over TLS. The 16-bit DDR2 / LPDDR2 controller plus EBI NAND boot make the MPU a self-contained Linux appliance, while the Gigabit Ethernet and three SD/MMC ports enable both wired backhaul and local storage. Hardware cryptographic accelerators cut the TLS handshake to milliseconds, important for constrained edge nodes that authenticate frequently. Compared with RPi-class SoMs, the ATSAMA5D36A-CU is supplied in industrial temperature grade and ships with a long-life Microchip product roadmap.
Recommended
Multimedia Consumer Devices
Consumer multimedia appliances - printer control panels, label printers, smart appliances - benefit from the ATSAMA5D36A-CU's hardware 2D engine that scales and blends camera input onto an attached LCD. The triple SDIO ports let the design accept Wi-Fi modules, eMMC, and SD cards simultaneously, while the Gigabit Ethernet MAC provides wired network connectivity. Industrial temperature grade means the same part covers both indoor consumer enclosures and semi-outdoor kiosks. Compared with a discrete GPU plus 32-bit MCU, the integrated 2D pipelines make UI rendering feel snappy at WVGA and remove cross-driver compatibility issues.
Recommended
Touch-Screen Operator Panels
Operator-interface terminals in factory automation rely on the ATSAMA5D36A-CU's built-in LCD controller and ISI block to drive both the screen and an optional camera for vision-assisted diagnostics. The 12-bit ADC samples analog potentiometers and analog joystick inputs as fall-back controls, while the HSIC ports drive high-speed companion chips such as image sensors. Linux4SAM supplies capacitive-touch drivers, and the GbE MAC backhauls status to the plant SCADA over PROFINET. Compared with a touchscreen HMI based on an MCU + external display controller, integrating the GPU onto the MPU reduces the I/O bus burden and lets CPU cycles go to control loop mathematics.
Recommended
Recommended Products Summary
Engineering reference data for ATSAMA5D36A-CU — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | ATSAMA5D36A-CN | ATSAMA5D35A-CU | ATSAMA5D34A-CU | ATSAMA5D27A-CU | ATSAMA5D28A-CU |
|---|---|---|---|---|---|---|
| Brand | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology |
| Package | 324-LFBGA (15x15) | 324-LFBGA (15x15) - same | 324-LFBGA (15x15) - same | 324-LFBGA (15x15) - same | 324-LFBGA (15x15) - same | 324-LFBGA (15x15) - same |
| Maximum CPU Clock | 536 MHz | 536 MHz | 536 MHz | 536 MHz | 500 MHz | 500 MHz |
| Internal SRAM | 128 KB | 128 KB | 128 KB | 128 KB | 128 KB | 128 KB |
| NEON Media Engine | No | No | No | Yes | No | No |
| Gigabit Ethernet | Yes (1x GMII/RGMII) | Yes | No | No | No | No |
| 10/100 Ethernet | Yes (1x RMII/RGMII) | Yes | Yes | Yes | Yes | Yes |
| External Memory Type | LPDDR/LPDDR2/DDR2 (16-bit) | LPDDR/LPDDR2/DDR2 | LPDDR/LPDDR2/DDR2 | LPDDR/LPDDR2/DDR2 | LPDDR2/LPDDR3/DDR3 | LPDDR2/LPDDR3/DDR3 |
| Operating Temperature | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C |
Key Differentiators
- Integrated hardware 2D graphics + GbE in a single Cortex-A5 MPU (vs ATSAMA5D34A-CU)
- Higher 536 MHz clock vs lower-tier 500 MHz SAMA5D2 (vs ATSAMA5D28A-CU)
- Both 16-bit LPDDR/DDR2 controller and 3 SD/MMC + 3 USB (vs ATSAMA5D35A-CU)
Design Notes
The ATSAMA5D36A-CU requires a precise power-up sequence: VDDPLL must come up first, followed by VDDUTMIC, then VDDUTMI, then VDDANA, with no more than 30 ms of overlap between rails. Use a Microchip MIC280 or an equivalent PMIC that exposes the same enable-chain pins. Hold NRST low until all rails are stable. Estimated maximum peak current on the 1.2 V rail is ~400 mA at 536 MHz with both Ethernet ports active; budget for 1 A peak transient capability on the buck regulator.
The 324-LFBGA at 15 x 15 mm uses a 0.8 mm ball pitch; route on a 4-layer PCB minimum with a continuous ground plane on layer 2 and a power island on layer 3. The DDR2 / LPDDR2 data, address, and command traces must be length-matched within 50 mils and routed on the top layer only over an unbroken ground plane. Place the external SDRAM chips on the same side as the MPU, less than 50 mm trace length, and add a 100 nF decoupling cap per power pin within 5 mm of the ball.
Do not forget to populate the external 32.768 kHz crystal on the RTC pins - omitting it prevents Linux from waking the system from ULP (ultra-low-power) mode. Configure JTAG pins as GPIO only after disabling boundary scan, otherwise JTAG will interpret rising edges on GPIO as debug requests. Ensure the boot pins (BMS, DIS) are strapped correctly before each POR; latched boot configuration determines whether NAND, NOR, SPI flash, or SD/MMC card is searched first for bootloader code.
Estimated: at maximum CPU utilization (536 MHz, both Ethernet ports active, LCD at full refresh) the device dissipates around 1.0 W. The LFBGA package has a typical theta-JA of approximately 25 C/W with a standard 4-layer JEDEC test board, implying a 25 C junction temperature rise above ambient. For sealed enclosures without forced airflow, derate ambient to 60 C max to keep Tj under 85 C for industrial operation.
Compliance Information
RoHS and REACH compliant per Microchip product page. Not AEC-Q100 qualified; choose ATSAMA5D36A-CUR-AUTO variants if automotive qualification is required. Lead-free and halogen-free packaging.
