EP1M350F672C7 - Mercury PLD FPGA 350K Gates | Intel/Altera
Teilenummer: EP1M350F672C7 ✗ Abgekündigt| Menge | Stückpreis | Gesamt |
|---|---|---|
| 1 | $95 | $95,00 |
| 10 | $86.4 | $864,00 |
| 100 | $78.5 | $7.850,00 |
| 500 | $71.2 | $35.600,00 |
| 1.000 | $65.8 | $65.800,00 |
EP1M350F672C7 Übersicht
A Programmable Logic Device (PLD) is a general term for any digital integrated circuit whose logic function is defined by the customer rather than the mask set. The Mercury family is built on a 0.18-micrometer SRAM-based CMOS process with an embedded 4-input LUT architecture and dual-port RAM blocks, allowing logic functions to be reconfigured in-system at any time. FPGAs sit at the top of the digital logic hierarchy: programmable logic > PLD > CPLD > FPGA > SRAM-based FPGA > Mercury family.
Key features include up to 350K usable gates, multiple embedded system blocks (ESBs), dedicated LVDS I/O support, and a clock management subsystem with up to four phase-locked loops (PLLs). The 672-pin FineLine BGA package exposes a high pin count to drive wide parallel buses and dozens of high-speed serial links, while the -7 speed grade designates a mid-range timing closure target for cost-sensitive commercial designs.
The Mercury architecture pairs logic elements with embedded memory blocks and dedicated multiplier support, allowing DSP-style datapaths to be implemented without consuming logic resources for arithmetic primitives. Multi-voltage I/O banks support interfacing to 3.3V, 2.5V, and 1.8V peripherals on the same die, simplifying mixed-voltage system design.
Typical applications include telecom line-card glue logic, high-speed serial protocol bridging, image preprocessing pipelines, and digital test instrumentation backplanes. The wide package makes it suitable as a system controller on PCI, PMC, and custom mezzanine cards in industrial and defense platforms.
When designing with this device, plan power sequencing for the 1.5V core and 3.3V I/O rails simultaneously, and ensure the JTAG chain is correctly ordered with any boundary-scan devices on the board. The FineLine BGA requires X-ray or careful optical inspection after reflow to verify sphere collapse.
This page consolidates distributor inventory signals, drop-in Mercury-family alternatives, and design notes not duplicated in the manufacturer datasheet, helping engineers shorten sourcing time and avoid cross-package pitfalls.
Drop-in-Alternativen für EP1M350F672C7 – gleiches Gehäuse, Pin-kompatibel. Bauteile mit anderem Gehäuse, die eine PCB-Überarbeitung erfordern, sind ausgeschlossen.
Varianten dieser Serie
Modelle derselben Serie, die drop-in-kompatibel sind mit EP1M350F672C7 (gleiche Bauform und Footprint) – abweichend in Package, Operating Temperature, Family, Speed Grade, Manufacturer.
Schnellvergleichstool – Wählen Sie Alternativbauteile für den Direktvergleich:
EP1M350F780C7
✅ Drop-In✓ Auf Lager
$162 / Stück
Datenblatt ansehen →EP1M350B780C7
✅ Drop-In ⚠️ Spezifikationen ungeprüft✓ Auf Lager
$92 / Stück
Datenblatt ansehen →EP1M350B780C6
✅ Drop-In ⚠️ Spezifikationen ungeprüft✓ Auf Lager
$125 / Stück
Datenblatt ansehen →EP1M350B780I6
✅ Drop-In ⚠️ Spezifikationen ungeprüft✓ Auf Lager
$145.5 / Stück
Datenblatt ansehen →EP1M350F780C5
✅ Drop-In✓ Auf Lager
$1303 / Stück
Datenblatt ansehen →EP1M350F672C7 Grenzwerte & elektrische Eigenschaften
| Device Family | Mercury PLD (APEX) |
| Manufacturer | Altera (acquired by Intel) |
| Typical Gate Count | 350,000 system gates |
| Embedded Memory | Embedded System Blocks (ESBs) |
| PLL Count | Up to 4 PLLs |
| Speed Grade | C7 (commercial, -7 speed) |
| Gehäuse | 672-ball FineLine BGA (FBGA) |
| Process Technology | 0.18 um SRAM CMOS |
| Logic Voltage | 1.5 V core |
| I/O Voltage Support | 3.3 V / 2.5 V / 1.8 V |
| LVDS Support | Yes (dedicated channels) |
| Configuration Method | SRAM-based, JTAG / EPC configuration devices |
| Betriebstemperatur | Commercial (0C to +85C) |
| RoHS-Status | Lead-free / RoHS Compliant |
EP1M350F672C7 672-ball fineline bga (fbga) Pinbelegungsleitfaden
Pinbelegung für EP1M350F672C7 (672-ball fineline bga (fbga)-Gehäuse). Dieser digitale IC umfasst GPIO, Kommunikationsschnittstellen (UART, SPI, I2C) und Versorgungspins. Alternative Pin-Funktionen und Konfigurationsoptionen entnehmen Sie dem Herstellerdatenblatt. Unverzichtbar für Embedded-System-Design und PCB-Layout.
Keine detaillierten Pinbelegungsdaten verfügbar für EP1M350F672C7.
Siehe die Datenblatt für die vollständige Pin-Konfiguration.
Typische Anwendungen
EP1M350F672C7 ist geeignet für 6 Anwendungs: Telecom Line-Card Glue Logic, High-Speed Serial Protocol Bridging, Image Preprocessing Pipelines, Digital Test Instrumentation Backplanes, Industrial Mezzanine Card Controller, Legacy Defense Avionics Sustainment.
Telecom Line-Card Glue Logic
The EP1M350F672C7's 350K-gate capacity and abundant LVDS-capable I/O make it well suited as a glue-logic controller on telecom line cards, where it bridges high-speed serial links to parallel backplane buses. With up to 4 PLLs and multi-voltage I/O banks (3.3V/2.5V/1.8V), it can fan out clocks and aggregate framer/mapper traffic without external PLL devices, reducing BOM. The 672-ball FBGA supports dozens of differential pairs needed for E1/T1, HDSL, and basic-rate ISLVDS links. Industrial-grade design margin allows deployment in temperature-controlled central-office racks. Place 0.1uF decoupling caps adjacent to every power ball, and route LVDS pairs with 100-ohm differential impedance and length matching within 5 mils.
Empfohlen
High-Speed Serial Protocol Bridging
With LVDS I/O and embedded system blocks (ESBs) that can be configured as dual-port RAM or FIFO buffers, the EP1M350F672C7 implements protocol converters between SPI, I2C, UART, and parallel LVDS streams. The 350K-gate budget accommodates 8-bit CRC engines, small RISC soft-cores, and protocol state machines in a single device. The -7 speed grade supports internal clock rates up to ~100 MHz, sufficient for Fast Ethernet MAC wrapping or basic RapidIO bridging. Use the PLLs to derive multiple baud-rate clocks from a single reference. Add an external configuration EPROM (EPC) so the device self-loads at power-up without a host processor.
Empfohlen
Image Preprocessing Pipelines
The Mercury family's ESBs can be cascaded into line buffers, enabling real-time image preprocessing such as thresholding, dilation, and convolution at video rates. The 350K-gate EP1M350F672C7 fits mid-resolution pipelines (e.g. 640x480 at 30 fps) where modest embedded multipliers suffice for simple kernels. LVDS I/O accepts camera-link or channel-link sensor data directly, while multi-voltage I/O drives standard TTL/CMOS image-capture ADCs. Pin-assign JTAG to a 10-pin header so design iterations can be downloaded in seconds during development. Use ESBs as dual-port RAM when implementing pixel FIFOs between camera and processor interfaces.
Empfohlen
Digital Test Instrumentation Backplanes
The 672-ball FBGA exposes enough I/O for a full PXI/VXI-style backplane controller with 32+ trigger lines, 16+ analog-monitor gates, and a parallel instrument bus. Embedded RAM blocks store calibration coefficients and pattern buffers for ATE applications, while the -7 speed grade maintains sub-100ns deterministic responses for real-time triggers. Multi-voltage I/O banks (3.3/2.5/1.8V) interconnect legacy CMOS, modern LVTTL, and lower-voltage ADCs on the same board. Use JTAG boundary scan for in-system test access to every BGA ball, but ensure the JTAG chain is correctly ordered with any scan-bridge ASICs.
Empfohlen
Industrial Mezzanine Card Controller
On PCI, PMC, and custom industrial mezzanine cards, the EP1M350F672C7 acts as the local bus master with enough logic capacity to implement scatter-gather DMA engines and 32-bit register interfaces. The 672-ball BGA's edge-density accommodates PMC-style 64-pin I/O connectors plus on-board DRAM address/data buses. -7 speed grade supports 33 MHz PCI with comfortable timing margin, while the embedded RAM buffers bus-master descriptors. Industrial-temperature parts in this family operate reliably in -40C to +85C chassis. Plan power sequencing so the 1.5V core and 3.3V I/O ramp together to avoid latch-up during hot-plug events.
Empfohlen
Legacy Defense Avionics Sustainment
Many defense platforms have Mercury-based designs in active service, where sustaining engineering requires replacement parts that are functionally and pin-compatible. The EP1M350F672C7's wide temperature range variants and rugged FBGA package suit avionics bay environments. Its deterministic SRAM-based configuration allows bitstream revision tracking for airworthiness certification. In sustainment roles, the part can be sourced through authorized brokers with date-code traceability. Cross-reference to B-step revisions (EP1M350B780C7) for improved errata. Pair with a watchdog supervisor and ECC memory if the application requires single-event-upset mitigation.
Empfohlen
Zusammenfassung der empfohlenen Produkte
Technische Referenzdaten für EP1M350F672C7 – Vergleich, Designhinweise und Compliance-Informationen.
Auswahlhilfe
Vergleich mit Alternativen
| Parameter | Dieses Produkt | EP1M350F780C7 | EP1M350B780C7 | EP1M350B780C6 | EP1M350B780I6 | EP1M350F780C5 |
|---|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera | Altera |
| Package | 672-ball FineLine BGA | 780-ball FineLine BGA | 780-ball FineLine BGA | 780-ball FineLine BGA | 780-ball FineLine BGA | 780-ball FineLine BGA |
| Device Family | Mercury PLD (APEX) | Mercury PLD (APEX) | Mercury PLD (APEX) | Mercury PLD (APEX) | Mercury PLD (APEX) | Mercury PLD (APEX) |
| System Gates | 350K | 350K | 350K | 350K | 350K | 350K |
| Speed Grade | -7 (C7) | -7 | -7 | -6 | -6 | -5 |
| Operating Temperature | Commercial (0C to +85C) | Commercial | Commercial | Commercial | Industrial | Commercial |
| Silicon Step | C-step | C-step | B-step | B-step | B-step | C-step |
| Lifecycle Status | NRND | NRND | NRND | NRND | NRND | NRND |
Wichtigste Unterscheidungsmerkmale
- Higher I/O count than same-die 672-ball baseline (vs. EP1M350F780C7)
- Mid-range speed grade for cost-sensitive commercial designs (vs. EP1M350F780C5)
- Improved silicon revision (B-step) for lower errata (vs. EP1M350B780C7)
Designhinweise
The Mercury FPGA requires simultaneous ramp of the 1.5V core and 3.3V I/O rails. Power sequencing violation can cause latch-up or permanent damage. Use a power-supply sequencer IC or place a Schottky steering network that ensures VCCINT never exceeds VCCIO by more than 2.5V during ramp. Decouple each power ball with a 0.1uF X7R ceramic plus a bulk 220uF tantalum at the supply entry point.
Estimated: at 100% toggle rate on all I/O at 100 MHz, the 672-FBGA Mercury dissipates approximately 3-5W. The FineLine BGA exposes a thermal pad under the package that should be soldered to a copper pour with thermal vias (9-16 vias, 0.3mm drill) to a backside heatsink plane. Without thermal management, junction temperature can exceed 100C in still air, triggering the on-die thermal diode warning.
Route LVDS differential pairs with 100-ohm differential impedance and intra-pair length matching within 5 mils. Keep clock PLL power supply isolated with a ferrite bead and 10uF + 0.1uF local decoupling. Provide 4-layer stack-up with continuous ground plane beneath the BGA - signal return paths depend on this reference. BGA escape requires microvia or 4-mil trace/space fabrication.
Do not program the configuration JTAG chain out of order - chain order must match the BSDL file exactly or Quartus/MAX+PLUS will fail to detect the device. Ensure MSEL pins select the correct configuration mode (AS, AP, PS, JTAG) with proper pull-up/pull-down resistors. Do not leave unused I/O floating - configure them as outputs driving low to minimize power and switching noise. Always read the silicon errata before final layout freeze.
Compliance-Informationen
RoHS-compliant per Altera product page and Alibaba broker listings (lead-free). REACH, halogen-free, and conflict-minerals declarations are not explicitly published; treat as unknown. Not AEC-Q100 qualified - this is a commercial-grade FPGA; industrial-temp variant (B780I6) is recommended for harsh-environment designs.