EP1M350F780C5 - 350K LE Mercury FPGA with 1.25 Gbps CDR | Altera
MPN: EP1M350F780C5 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $1861 | $1,861.00 |
| 10 | $1675 | $16,750.00 |
| 100 | $1489 | $148,900.00 |
| 500 | $1395 | $697,500.00 |
| 1,000 | $1303 | $1,303,000.00 |
Drop-in alternatives for EP1M350F780C5 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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EP1M350F780-C7
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View Datasheet →EP1M350F78016
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View Datasheet →EP1M350F672C7N
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View Datasheet →EP1M350F780C5 Maximum Ratings & Electrical Characteristics
| Device Family | Mercury |
| Logic Elements (approx.) | 350,000 |
| User I/O Pins | 486 |
| Embedded Transceivers | High-speed CDR channels up to 1.25 Gbps |
| Core Voltage | 1.71 V to 1.89 V |
| Speed Grade | C5 (commercial, fastest) |
| Operating Temperature | 0 °C to +85 °C (TJ) |
| Package | 780-ball FCBGA (29 mm x 29 mm, 1 mm pitch) |
| Supply Voltage Range | 1.71 V ~ 1.89 V |
| Supplier Device Package | 780-FBGA (29x29) |
| Package / Case | 780-BBGA, FCBGA |
| Series | Mercury |
| Mounting Type | Surface Mount |
| RoHS Status | Non-compliant (per some distributor listings) |
| Lifecycle Status | Not Recommended for New Designs (NRND) |
EP1M350F780C5 780-bbga, fcbga Pin Configuration Guide
Complete pinout information for EP1M350F780C5 (780-bbga, fcbga package) with 486 pins. This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EP1M350F780C5.
Refer to the datasheet for full pin configuration.
Estimated pin count: 486 pins (digital package)
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EP1M350F780C5 is suitable for 6 applications: High-Speed Serial Backplane Bridge, Gigabit Ethernet Line Card Aggregation, Fibre Channel Storage Controller, Telecom Aggregation and Protocol Conversion, Industrial Test and Measurement Equipment, Legacy ASIC/ASSP Replacement in Maintenance Programs.
High-Speed Serial Backplane Bridge
The EP1M350F780C5 is purpose-built for backplane bridging because its integrated 1.25 Gbps CDR transceivers eliminate the need for external SerDes in many legacy backplane designs. The 350K logic elements provide enough fabric to implement protocol-conversion state machines, FIFOs, and PCS glue between SPI-4.2, SFI-4.1, or proprietary parallel interfaces and the multi-gigabit serial links. Designers place the device on the line card with AC-coupled serial traces to the backplane connector, using the on-chip CDR to recover clock and data without an external PHY. The 780-FBGA footprint supports controlled-impedance escape routing on standard FR-4 backplanes, and the 1.8 V core simplifies power tree design compared to 1.2 V modern parts.
Recommended
Gigabit Ethernet Line Card Aggregation
In gigabit Ethernet aggregation switches, the EP1M350F780C5's combination of multi-gigabit transceivers and a large LUT fabric allows designers to implement multiple MACs, classifier engines, and traffic shapers on a single die. Each 1.25 Gbps CDR channel can carry a gigabit Ethernet link, and 486 user I/O pins give access to multiple parallel datastreams to external TCAMs, RLDRAMs, or network processors. The C5 speed grade is critical for tight inter-packet timing at line rate, and the 780-FBGA package provides adequate thermal headroom when paired with the recommended thermal management footprint. This part is typically placed at the heart of legacy enterprise switching products that have not yet migrated to Stratix-class devices.
Recommended
Fibre Channel Storage Controller
Fibre Channel at 1 Gbps operates well within the EP1M350F780C5's 1.25 Gbps CDR envelope, making this device a natural fit for legacy Fibre Channel storage controllers and HBAs. The 350K logic elements can host the FC protocol engine, SCSI/ATA bridging logic, and DMA engines that move payloads to system memory, while the integrated transceivers handle the FC-0 and FC-1 layers directly. Designers save bill-of-materials cost and board area by avoiding an external SerDes plus encoder/decoder pair. The commercial 0-85 °C junction range covers typical server-room environments, and the FCBGA package's thermal characteristics are well documented in the Mercury device handbook.
Recommended
Telecom Aggregation and Protocol Conversion
Telecom equipment manufacturers adopted the Mercury family for protocol conversion between legacy TDM/ATM fabrics and emerging packet-based switching. The EP1M350F780C5 supports multiple 1.25 Gbps links alongside a deep LUT fabric, allowing designers to terminate serial backplane traffic, de/packetize it, and forward it to parallel framers or network processors. The 486 user I/O pins are well-matched to UTOPIA / POS-PHY Level 3/4 bus widths to external framers. Designers should follow Mercury power-sequencing guidelines carefully because the 1.8 V core and I/O banks must ramp in a defined order to prevent permanent damage.
Recommended
Industrial Test and Measurement Equipment
Test and measurement instruments such as protocol analyzers, BERT testers, and high-speed data recorders benefit from the EP1M350F780C5's combination of multi-gigabit serial I/O and large parallel fabric. Designers can build custom pattern generators, error detectors, and protocol-aware capture logic that connect directly to 1.25 Gbps serial links under test, with the parallel fabric handling triggering, timestamping, and host-side data movement. The 780-FBGA is straightforward to integrate on a 6-layer or 8-layer test-instrument mainboard, and the C5 speed grade supports deterministic timing for compliance test suites. When targeting industrial (-40 °C to +100 °C) environments, designers should select the industrial-temperature EP1M350F78016 variant.
Recommended
Legacy ASIC/ASSP Replacement in Maintenance Programs
When a discontinued ASIC or ASSP drives a critical end-product, the EP1M350F780C5 is often used as an FPGA-based form-fit-function replacement because the Mercury family's 1.25 Gbps transceivers and 486 I/O pins can reproduce the I/O signature of many older networking ASICs. The C5 speed grade helps close timing on replacement designs, and the 780-FBGA footprint can be laid out to match the legacy ASIC's BGA pattern when board spin is not feasible. Designers should treat this use case as a maintenance activity only; Altera's NRND recommendation is to migrate active programs to Stratix IV GX or later families with active PCN support and modern transceivers.
Recommended
Recommended Products Summary
Engineering reference data for EP1M350F780C5 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EP1M350F780-C7 | EP1M350F78016 | EP1M350F672C7N |
|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera |
| Package | 780-FBGA (29x29) | 780-FBGA (29x29) - same | 780-FBGA (29x29) - same | 672-BGA - different, smaller |
| Logic Elements (approx.) | 350,000 | 350,000 | 350,000 | [DATA_NEEDED] |
| Speed Grade | C5 (fastest commercial) | C7 (slower, ~15-20% lower fMAX) | [DATA_NEEDED] | C7 |
| User I/O Pins | 486 | 486 | 486 | fewer than 486 (smaller package) |
| Transceiver Rate | up to 1.25 Gbps CDR | up to 1.25 Gbps CDR | up to 1.25 Gbps CDR | up to 1.25 Gbps CDR |
| Core Voltage | 1.71 V to 1.89 V | 1.71 V to 1.89 V | 1.71 V to 1.89 V | 1.71 V to 1.89 V |
| Operating Temperature | 0 °C to +85 °C (TJ) | 0 °C to +85 °C (TJ) | Industrial (-40 °C to +100 °C) | 0 °C to +85 °C (TJ) |
| Lifecycle Status | NRND | NRND | NRND | NRND |
| Reference Unit Price (qty 1, USD) | 1,861.00 | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] |
Key Differentiators
- Integrated 1.25 Gbps CDR transceivers (vs EP1M350F780-C7)
- Fastest commercial speed grade (vs EP1M350F78016)
- High user I/O count (vs EP1M350F672C7N)
- Mature Mercury toolchain (vs Newer Altera/Intel families)
Design Notes
Estimated: The Mercury family's 1.8 V core and I/O rails must ramp in the sequence specified in the Mercury device handbook. Designers commonly use a four-rail sequencer (e.g., LTC2928 or equivalent) to enforce VCCINT before VCCIO and clamp the POR pin until all rails are stable. Skipping sequencing risks latch-up; budget for the sequencer and its supporting passives in the BOM. Core current at full fabric utilization on a 350K-LE device can exceed several amps, so plan for at least 4 oz copper pours or external copper heatsinks directly under the FCBGA thermal pad.
The 780-FBGA at 1 mm pitch requires a multilayer PCB stack-up with microvias or laser-drilled blind/buried vias to reliably escape all balls. A 6-layer 1-6-1 stack-up is the minimum; an 8-layer 1-5-2 design gives better signal-integrity margin for the multi-gigabit serial traces. Matched-impedance (100 ohm differential for serial links, 50 ohm single-ended for control) must be verified with a 3D EM field solver before tape-out; do not rely on rule-of-thumb calculators for BGA escapes.
Configuration bitstream storage: the EP1M350F780C5 requires an external configuration PROM (typically EPC16 or EPC8) or a microcontroller to load the SRAM configuration at power-up. Designers sometimes forget to size the PROM correctly for compressed bitstreams or fail to add JTAG headers for in-system programming. Also note the NRND status of the configuration PROMs themselves - if your PROM is also NRND, plan a migration path before your program goes into production.
AC-coupling capacitors on the 1.25 Gbps CDR serial links must be placed within 200 mil of the BGA balls and use 0402 or smaller packages to minimize stub length. Use 0.1 µF X7R capacitors rated for at least 6.3 V to handle bias transients. Reference-plane stitching vias should be placed at least every λ/20 along the serial traces to suppress return-path discontinuities. Run post-layout simulation with IBIS-AMI models of the Mercury transceiver before committing to fabrication.
Compliance Information
RoHS non-compliance reported by alterachips.com distributor listing; reach/lead-free/halogen-free data not present in Verified Web Data and marked unknown. AEC-Q100 not applicable - this is an FPGA, not an automotive-grade IC. Conflict-minerals status not stated.
