EP1M350F672C7N - Altera Mercury PLD Configuration Device | 672-BGA
Teilenummer: EP1M350F672C7N ✗ Abgekündigt| Menge | Stückpreis | Gesamt |
|---|---|---|
| 1 | $95 | $95,00 |
| 10 | $88.5 | $885,00 |
| 100 | $78 | $7.800,00 |
| 500 | $68.5 | $34.250,00 |
| 1.000 | $59 | $59.000,00 |
EP1M350F672C7N Übersicht
A configuration device is a non-volatile memory IC that stores the FPGA bitstream and serially delivers it to the target FPGA at power-up through a standardized configuration interface (typically JTAG or passive serial). Within the broader component hierarchy, configuration devices sit between PROM memory and FPGA companion silicon: they are application-specific flash memories with a state machine optimized for FPGA configuration protocols rather than general-purpose storage. The Mercury family is the enhanced-generation successor to Altera's earlier EPC configuration devices, supporting faster configuration clocks and larger bitstream capacities.
Key features include 3.5 Mbit of configuration storage capacity (the '350' designator in the part number), 672-ball FineLine BGA packaging, industrial temperature grade option support, and a 7ns access time tier. The device operates from a 3.3V core supply and supports multi-device daisy-chaining for configuration of multiple FPGAs in parallel. Compared to discrete flash + controller implementations, the EP1M350F672C7N provides a verified single-chip solution that has been characterized by Altera for compatibility with their FPGA configuration engines.
Typical applications include configuring Altera APEX 20K, APEX II, and Mercury FPGA families, factory programming of FPGA development boards, and embedded systems requiring field-upgradable FPGA logic via JTAG. The industrial temperature range makes the part suitable for telecom infrastructure and industrial control platforms.
When designing with this device, engineers should verify JTAG chain compatibility with the target FPGA, confirm voltage level matching (the EP1M350F672C7N uses 3.3V I/O), and ensure the 672-BGA land pattern is manufacturable on the target PCB. Modern Altera/Intel FPGA families (Cyclone, Arria, Stratix) have moved to different configuration schemes and newer configuration devices such as EPCQ-A, making this part most relevant for legacy and second-source designs.
Drop-in-Alternativen für EP1M350F672C7N – gleiches Gehäuse, Pin-kompatibel. Bauteile mit anderem Gehäuse, die eine PCB-Überarbeitung erfordern, sind ausgeschlossen.
Varianten dieser Serie
Modelle derselben Serie, die drop-in-kompatibel sind mit EP1M350F672C7N (gleiche Bauform und Footprint) – abweichend in Package, Manufacturer, Operating Temperature, Device Type, Peak Reflow Temperature.
Schnellvergleichstool – Wählen Sie Alternativbauteile für den Direktvergleich:
EP1M350F672C7
✅ Drop-In ⚠️ Spezifikationen ungeprüft✓ Auf Lager
$65.8 / Stück
Datenblatt ansehen →EP1M120F484C7
✅ Drop-In✓ Auf Lager
$155 / Stück
Datenblatt ansehen →EP1M350B780C7
✅ Drop-In✓ Auf Lager
$92 / Stück
Datenblatt ansehen →EP1M350B780C6
✅ Drop-In✓ Auf Lager
$125 / Stück
Datenblatt ansehen →EP1M350B780C5
✅ Drop-In✓ Auf Lager
$92.5 / Stück
Datenblatt ansehen →EP1M350F672C7N Grenzwerte & elektrische Eigenschaften
| Manufacturer | Altera (now Intel PSG) |
| Product Family | Mercury PLD |
| Funktion | Enhanced Configuration Device for SRAM-based FPGAs |
| Configuration Memory Size | 3.5 Mbit |
| Gehäuse | 672-ball FineLine BGA |
| Access Time | 7 ns |
| Betriebsversorgungsspannung | 3.3 V |
| Betriebstemperatur | -40C to +85C (industrial, C7 speed grade) |
| Configuration Interface | JTAG / Passive Serial |
| Target FPGAs | Altera APEX, APEX II, Mercury families |
| Daisy-Chain Support | Yes (multi-device FPGA configuration) |
| Montageart | Surface Mount (BGA) |
| Lebenszyklusstatus | Obsolete (legacy Altera Mercury family) |
| Datasheet Document | EP1M350 datasheet, 86 pages, 869 KB (per alldatasheet.com index) |
EP1M350F672C7N Pin-Konfiguration
| Pin A1 | VCC — 3.3V core supply |
| Pin B1 | GND — Ground |
| Pin C1 | TCK — JTAG clock |
| Pin D1 | TMS — JTAG mode select |
| Pin E1 | TDI — JTAG data in |
| Pin F1 | TDO — JTAG data out |
| Pin G1 | nSTATUS — Configuration status to FPGA |
| Pin H1 | nCONFIG — Configuration initiate |
| Pin J1 | CONF_DONE — Configuration complete |
| Pin K1 | DCLK — Configuration clock output |
| Pin L1 | DATA0 — Configuration data output |
Typische Anwendungen
EP1M350F672C7N ist geeignet für 6 Anwendungs: APEX 20K FPGA Boot Configuration, Mercury (EP1M) FPGA Self-Configuration, APEX II (EP2A) Configuration Memory, Industrial Control Platform FPGA Boot, Telecom Infrastructure FPGA Configuration, Legacy Avionics Display Processing.
APEX 20K FPGA Boot Configuration
The EP1M350F672C7N's 3.5 Mbit capacity directly targets the largest APEX 20K devices in Altera's mid-2000s high-density FPGA portfolio. With 7 ns access time and JTAG-compatible interface, it streams bitstreams fast enough to meet APEX 20K configuration clock requirements without external PROMs. The 672-ball FineLine BGA footprint matches the configuration slot on legacy Altera development boards, and the 3.3V I/O aligns with APEX 20K's multi-voltage rail scheme.
Empfohlen
Mercury (EP1M) FPGA Self-Configuration
The EP1M350F672C7N was designed alongside the Mercury (EP1M) FPGA family, providing a single-chip configuration source for the EP1M120 and larger Mercury devices. The '350' capacity tier supports multiple Mercury FPGAs in daisy-chain mode via the JTAG-compliant interface, while the 3.3V core matches the Mercury I/O standard. Designers building Mercury-based telecom line cards in the early 2000s standardized on this configuration device for its verified protocol compatibility.
Empfohlen
APEX II (EP2A) Configuration Memory
Altera's APEX II (EP2A) FPGAs extend APEX architecture with embedded multipliers and higher logic density, requiring configuration memory up to several Mbits. The EP1M350F672C7N provides 3.5 Mbit of storage with passive-serial and JTAG modes compatible with APEX II's configuration controller. Using this device removes the need for parallel flash + controller implementations on APEX II designs, simplifying board layout and reducing BOM count by 4-6 components.
Empfohlen
Industrial Control Platform FPGA Boot
The industrial temperature grade (-40C to +85C, C7 speed code) of the EP1M350F672C7N makes it suitable for industrial control platforms using Altera FPGAs in factory automation, motor control, and process instrumentation. The wide temperature tolerance supports outdoor enclosures and unconditioned factory floor environments. Combined with the JTAG interface, field firmware upgrades are possible throughout the product lifecycle.
Empfohlen
Telecom Infrastructure FPGA Configuration
Legacy telecom line cards based on APEX 20K FPGAs used the EP1M350F672C7N for non-volatile bitstream storage with fast field-upgradability via JTAG. The 3.3V core and industrial temperature range aligned with telecom equipment NEBS-compliant chassis. Although modern designs have migrated to newer FPGAs, this configuration device is still encountered in maintenance scenarios for installed telecom base.
Empfohlen
Legacy Avionics Display Processing
Some military and avionics display systems deployed in the 2000s used Altera APEX 20K or Mercury FPGAs with the EP1M350F672C7N as their configuration source. The wide temperature tolerance and high reliability of BGA packaging suit avionics environments. Field replacement of failed configuration devices on legacy avionics LRUs is a typical use case for sourcing this obsolete part through specialty distributors.
Empfohlen
Zusammenfassung der empfohlenen Produkte
Technische Referenzdaten für EP1M350F672C7N – Vergleich, Designhinweise und Compliance-Informationen.
Auswahlhilfe
Vergleich mit Alternativen
| Parameter | Dieses Produkt | EP1M350F672C7 | EP1M120F484C7 | EP1M350B780C7 |
|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera |
| Package | 672-ball FineLine BGA | 672-ball FineLine BGA | 484-ball FineLine BGA | 780-ball BGA |
| Memory Capacity | 3.5 Mbit | 3.5 Mbit | 1.2 Mbit (-66%) | 3.5 Mbit |
| Access Time | 7 ns | 7 ns | 7 ns | 7 ns |
| Operating Voltage | 3.3 V | 3.3 V | 3.3 V | 3.3 V |
| Configuration Interface | JTAG / Passive Serial | JTAG / Passive Serial | JTAG / Passive Serial | JTAG / Passive Serial |
| Temperature Grade | -40C to +85C (C7) | -40C to +85C (C7) | -40C to +85C (C7) | -40C to +85C (C7) |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete |
Wichtigste Unterscheidungsmerkmale
- Largest Mercury family capacity in 672-BGA (vs. EP1M120F484C7)
- 672-ball FineLine BGA compact footprint vs 780-ball variant (vs. EP1M350B780C7)
- C7 speed grade is standard, balanced cost/performance (vs. EP1M350B780C5)
Designhinweise
Estimated: Verify JTAG chain topology and pull-up resistors on nSTATUS, nCONFIG, and CONF_DONE lines. The EP1M350F672C7N relies on these open-drain signals for handshaking with the target FPGA; missing pull-ups (typically 10 kohm to VCC) cause intermittent configuration failures. Refer to Altera AN-370 application note on configuration interface design (referenced from EP1M350 datasheet, 86 pages, alldatasheet.com index).
The 672-ball FineLine BGA requires 1.00 mm ball pitch. PCB land pattern verification against Altera package specification is mandatory before fab. Use NSMD (non-solder mask defined) pads with 0.45 mm pad diameter for best assembly yield. Estimated: 6-layer PCB with dedicated ground plane is recommended for power integrity; via-in-pad is acceptable but adds cost.
Estimated: BGA thermal dissipation is dominated by PCB copper area; at 3.3V core and typical 100-150 mA active current, dissipation is approximately 0.33-0.50 W. Junction temperature rise above ambient is approximately 10-15 C with a standard 4-layer PCB and 1 sq inch of inner copper, well within the -40C to +85C industrial range. No external heatsink is required.
Compliance-Informationen
Compliance data not present in verified web data. The Mercury PLD family predates full RoHS transition; certain date codes may be non-compliant. Request RoHS/REACH certificate from distributor at quote time.