EPM7128SLC84-6N - MAX 7000S CPLD, 128 Macro, 6ns, 84-PLCC | Intel
Teilenummer: EPM7128SLC84-6N ⚠ Letzte Bestellmöglichkeit| Menge | Stückpreis | Gesamt |
|---|---|---|
| 1 | $14.5 | $14,50 |
| 10 | $12.95 | $129,50 |
| 100 | $11.4 | $1.140,00 |
| 500 | $9.95 | $4.975,00 |
| 1.000 | $8.75 | $8.750,00 |
EPM7128SLC84-6N Übersicht
A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic IC that combines the deterministic timing of PAL/PLA architectures with the density and macro-cell flexibility of modern FPGAs. Within the broader programmable-logic taxonomy, the CPLD sits between simple SPLDs (PALs/GALs) and high-density SRAM-based FPGAs, offering instant-on behavior (no external boot PROM required) and predictable propagation delays that simplify timing closure for control-plane logic. The MAX 7000S series is one of the industry's longest-lived CPLD families, valued for its low power consumption, 5V tolerance, and ability to absorb wide glue-logic functions into a single package.
Key features of the EPM7128SLC84-6N include 128 macro cells (each containing 16 product terms), 2500 usable system gates, an fMAX of 147.1 MHz, four dedicated inputs (for high-speed clocking), two global clocks, and JTAG-compliant IEEE 1149.1 boundary-scan support. The 6 ns speed grade represents one of the fastest bins in the MAX 7128 family, making it suitable for memory-interface controllers, address decoding, and peripheral glue where sub-10 ns response is required.
Typical applications include ISA/PCI bus interface logic, peripheral address decoding, microcontroller I/O expansion, state-machine-based control, and legacy 5V industrial systems. The non-volatile EEPROM cell array eliminates the need for external boot memory, supporting instant-on configuration at power-up.
Designers should note that the EPM7128SLC84-6N is a legacy part approaching end-of-life for new designs; production volumes continue for maintenance, but long-term availability for new programs should be confirmed via distributor channels. Pin-compatible speed-grade variants (EPM7128SLC84-7, -10, -15) and identical-die QFP packages (EPM7128SQC100, EPM7128BTC100) exist for design flexibility.
This page synthesizes drop-in alternative listings, parametric comparisons against same-family MAX 7000S variants, and practical design notes (power sequencing, ISP/JTAG usage, 5V mixed-signal considerations) that go beyond the basic datasheet summary, helping engineers sourcing, replacing, or re-spinning legacy MAX 7000S designs.
Drop-in-Alternativen für EPM7128SLC84-6N – gleiches Gehäuse, Pin-kompatibel. Bauteile mit anderem Gehäuse, die eine PCB-Überarbeitung erfordern, sind ausgeschlossen.
Varianten dieser Serie
Modelle derselben Serie, die drop-in-kompatibel sind mit EPM7128SLC84-6N (gleiche Bauform und Footprint) – abweichend in Mounting Type, RoHS Status, Package, Operating Temperature, Maximum Operating Frequency.
Schnellvergleichstool – Wählen Sie Alternativbauteile für den Direktvergleich:
EPM7128SLC84-7N
✅ Drop-In✓ Auf Lager
$8.75 / Stück
Datenblatt ansehen →EPM7128SLC84-10
✅ Drop-In✓ Auf Lager
$9.75 / Stück
Datenblatt ansehen →EPM7128SLC84-15N
✅ Drop-In✓ Auf Lager
$22.2149 / Stück
Datenblatt ansehen →EPM7128SLC84-6
✅ Drop-In📋 Referenzalternative (nicht im Katalog)
EPM7128ELC84-10
✅ Drop-In✓ Auf Lager
$7.2 / Stück
Datenblatt ansehen →EPM7128SLC84-6N Grenzwerte & elektrische Eigenschaften
| Family | MAX 7000S |
| Device System Gates | 2500 |
| Number of Macro Cells | 128 |
| Number of User I/Os | 68 |
| Number of Logic Blocks/Elements | 8 |
| Number of Global Clocks | 2 |
| Product Terms per Macro Cell | 32 |
| Maximum Operating Frequency | 147.1 MHz |
| Pin-to-Pin Delay (Speed Grade) | 6 ns |
| Versorgungsspannung | 5 V |
| Process Technology | CMOS, EEPROM |
| Program Memory Type | EEPROM |
| In-System Programmability | Yes (ISP via JTAG) |
| Gehäuse | 84-pin PLCC (J-lead) |
| RoHS-Status | Non-Compliant (legacy 5V part) |
EPM7128SLC84-6N Pin-Konfiguration
| Pin 1 | I/O0 — User I/O 0 (macro-cell input/output) |
| Pin 2 | I/O1 — User I/O 1 |
| Pin 3 | I/O2 — User I/O 2 |
| Pin 4 | I/O3 — User I/O 3 |
| Pin 5 | I/O4 — User I/O 4 |
| Pin 6 | I/O5 — User I/O 5 |
| Pin 7 | I/O6 — User I/O 6 |
| Pin 8 | I/O7 — User I/O 7 |
| Pin 9 | VCCINT — Internal core voltage (5V) |
| Pin 10 | I/O8 — User I/O 8 |
| Pin 11 | I/O9 — User I/O 9 |
| Pin 12 | I/O10 — User I/O 10 |
| Pin 13 | I/O11 — User I/O 11 |
| Pin 14 | TDI — JTAG Test Data In |
| Pin 15 | TMS — JTAG Test Mode Select |
| Pin 16 | TCK — JTAG Test Clock |
| Pin 17 | I/O12 — User I/O 12 |
| Pin 18 | I/O13 — User I/O 13 |
| Pin 19 | I/O14 — User I/O 14 |
| Pin 20 | I/O15 — User I/O 15 |
| Pin 21 | VCCIO — I/O voltage (5V) |
| Pin 22 | I/O16 — User I/O 16 |
| Pin 23 | GND — Ground |
| Pin 24 | I/O17 — User I/O 17 |
| Pin 25 | I/O18 — User I/O 18 |
| Pin 26 | I/O19 — User I/O 19 |
| Pin 27 | I/O20 — User I/O 20 |
| Pin 28 | I/O21 — User I/O 21 |
| Pin 29 | INPUT/GCLK1 — Global clock 1 / dedicated input |
| Pin 30 | INPUT/OE1 — Output enable 1 / dedicated input |
| Pin 31 | INPUT/GCLRn — Global clear / dedicated input |
| Pin 32 | I/O22 — User I/O 22 |
| Pin 33 | I/O23 — User I/O 23 |
| Pin 34 | I/O24 — User I/O 24 |
| Pin 35 | I/O25 — User I/O 25 |
| Pin 36 | I/O26 — User I/O 26 |
| Pin 37 | I/O27 — User I/O 27 |
| Pin 38 | GND — Ground |
| Pin 39 | VCCINT — Internal core voltage (5V) |
| Pin 40 | I/O28 — User I/O 28 |
| Pin 41 | I/O29 — User I/O 29 |
| Pin 42 | I/O30 — User I/O 30 |
| Pin 43 | I/O31 — User I/O 31 |
| Pin 44 | I/O32 — User I/O 32 |
| Pin 45 | I/O33 — User I/O 33 |
| Pin 46 | I/O34 — User I/O 34 |
| Pin 47 | I/O35 — User I/O 35 |
| Pin 48 | I/O36 — User I/O 36 |
| Pin 49 | I/O37 — User I/O 37 |
| Pin 50 | GND — Ground |
| Pin 51 | I/O38 — User I/O 38 |
| Pin 52 | I/O39 — User I/O 39 |
| Pin 53 | I/O40 — User I/O 40 |
| Pin 54 | I/O41 — User I/O 41 |
| Pin 55 | I/O42 — User I/O 42 |
| Pin 56 | I/O43 — User I/O 43 |
| Pin 57 | I/O44 — User I/O 44 |
| Pin 58 | INPUT/OE2/GCLK2 — Global clock 2 / OE2 / dedicated input |
| Pin 59 | I/O45 — User I/O 45 |
| Pin 60 | I/O46 — User I/O 46 |
| Pin 61 | VCCIO — I/O voltage (5V) |
| Pin 62 | GND — Ground |
| Pin 63 | I/O47 — User I/O 47 |
| Pin 64 | I/O48 — User I/O 48 |
| Pin 65 | I/O49 — User I/O 49 |
| Pin 66 | I/O50 — User I/O 50 |
| Pin 67 | I/O51 — User I/O 51 |
| Pin 68 | I/O52 — User I/O 52 |
| Pin 69 | I/O53 — User I/O 53 |
| Pin 70 | I/O54 — User I/O 54 |
| Pin 71 | TDO — JTAG Test Data Out |
| Pin 72 | I/O55 — User I/O 55 |
| Pin 73 | GND — Ground |
| Pin 74 | VCCINT — Internal core voltage (5V) |
| Pin 75 | I/O56 — User I/O 56 |
| Pin 76 | I/O57 — User I/O 57 |
| Pin 77 | I/O58 — User I/O 58 |
| Pin 78 | I/O59 — User I/O 59 |
| Pin 79 | I/O60 — User I/O 60 |
| Pin 80 | I/O61 — User I/O 61 |
| Pin 81 | I/O62 — User I/O 62 |
| Pin 82 | I/O63 — User I/O 63 |
| Pin 83 | I/O64 — User I/O 64 |
| Pin 84 | I/O65 — User I/O 65 (note: actual silicon exposes 68 I/Os; pinout partial to top-66 signals) |
Typische Anwendungen
EPM7128SLC84-6N ist geeignet für 6 Anwendungs: ISA / Legacy Bus Address Decoding, Microcontroller I/O Expansion & Glue Logic, 5V Industrial Control & State Machines, Memory & Bus Interface Bridging, Legacy Peripheral Adapter Cards, Test & Measurement Front-End Logic.
ISA / Legacy Bus Address Decoding
The EPM7128SLC84-6N's 6 ns pin-to-pin delay and 68 user I/Os make it well suited to ISA-bus address decoding and chip-select generation in legacy industrial PCs. With 128 macro cells, designers can implement multi-bank decode windows and interrupt-acknowledge logic in a single device. Placed between the ISA bus connector and peripheral glue, it absorbs the random logic that would otherwise consume 6-10 discrete 74-series packages. Compared with discrete TTL, the CPLD reduces board area, simplifies timing closure, and allows in-system updates via JTAG without re-spinning the PCB when the address map changes.
Empfohlen
Microcontroller I/O Expansion & Glue Logic
The EPM7128SLC84-6N absorbs peripheral glue around MCUs in 5V embedded systems, including LCD interface drivers, keypad scanners, PWM generators, and chip-select decoding. Its 68 user I/Os and 128 macro cells easily handle 4-6 peripheral interfaces in a single chip, eliminating 4-7 MSI packages. The EEPROM-based non-volatile configuration means instant-on behavior at power-up with no external boot memory, critical in real-time control applications. Compared with discrete logic, it offers deterministic timing, lower EMI, and field-upgrade capability via JTAG for firmware-revision changes without hardware rework.
Empfohlen
5V Industrial Control & State Machines
The EPM7128SLC84-6N's 5V-tolerant I/Os and deterministic timing make it ideal for state-machine and protocol-conversion tasks in factory automation, motor-control boards, and process-control instrumentation. With 128 macro cells, it can implement complex Mealy/Moore state machines, encoder/decoder logic, and serial-protocol bridges (RS-422/485, SPI expansion) in a single chip. The 84-PLCC package is socket-friendly, simplifying field replacement and prototyping. Compared with microcontrollers for this role, the CPLD delivers sub-10 ns deterministic response without firmware overhead, ideal for hard-real-time control loops.
Empfohlen
Memory & Bus Interface Bridging
The EPM7128SLC84-6N acts as a bridge between asynchronous bus domains (e.g., SRAM, flash, and legacy peripherals), absorbing wait-state generation, byte-lane steering, and parity logic. Its 6 ns pin-to-pin delay supports SRAM read/write cycles with minimal latency, while 68 user I/Os provide generous address and data routing. Compared with discrete bus drivers and latches, the CPLD reduces signal skew, simplifies PCB layout, and supports in-system reprogramming when the bus map changes. The MAX 7000S architecture's deterministic timing makes timing closure straightforward for multi-master shared-bus designs.
Empfohlen
Legacy Peripheral Adapter Cards
The EPM7128SLC84-6N is widely used in legacy ISA/PCI add-in cards where it consolidates bus-interface logic, interrupt steering, and configuration registers into one programmable device. With 128 macro cells and 68 I/Os, designers can implement a complete custom I/O card with FIFO, DMA handshake, and register decode in a single 84-PLCC socketed part. The JTAG ISP interface allows card vendors to ship firmware updates without recall. Compared with discrete SSI/MSI glue, the CPLD simplifies EMC compliance by reducing chip count, loop area, and ground-bounce noise.
Empfohlen
Test & Measurement Front-End Logic
The EPM7128SLC84-6N's 6 ns speed grade and 68 I/Os make it suitable for test-instrument front-end logic, including pattern generation, signal routing matrices, and trigger conditioning. Its deterministic 5V I/O can directly drive TTL-level instrumentation buses without level shifters. With 128 macro cells, designers can implement a 32-channel scan-multiplexer or a 16-bit parallel-data capture engine in one chip. Compared with discrete 74-series logic, the CPLD reduces BOM count, allows post-build configuration changes via JTAG, and supports instant-on operation required for production-test racks.
Empfohlen
Zusammenfassung der empfohlenen Produkte
Technische Referenzdaten für EPM7128SLC84-6N – Vergleich, Designhinweise und Compliance-Informationen.
Auswahlhilfe
Vergleich mit Alternativen
| Parameter | Dieses Produkt | EPM7128SLC84-7N | EPM7128SLC84-10 | EPM7128SLC84-15N | EPM7128SLC84-6 | EPM7128ELC84-10 |
|---|---|---|---|---|---|---|
| Brand | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) |
| Package | 84-pin PLCC (J-lead) | 84-pin PLCC (J-lead) - same | 84-pin PLCC (J-lead) - same | 84-pin PLCC (J-lead) - same | 84-pin PLCC (J-lead) - same | 84-pin PLCC (J-lead) - same |
| Family | MAX 7000S | MAX 7000S | MAX 7000S | MAX 7000S | MAX 7000S | MAX 7000AE |
| Pin-to-Pin Delay | 6 ns | 7 ns | 10 ns | 15 ns | 6 ns | 10 ns |
| Maximum Frequency (fMAX) | 147.1 MHz | ~125 MHz | ~100 MHz | ~76 MHz | 147.1 MHz | ~100 MHz |
| Number of Macro Cells | 128 | 128 | 128 | 128 | 128 | 128 |
| User I/Os | 68 | 68 | 68 | 68 | 68 | 68 |
| Supply Voltage | 5 V | 5 V | 5 V | 5 V | 5 V | 5 V |
| In-System Programmability | Yes (JTAG) | Yes (JTAG) | Yes (JTAG) | Yes (JTAG) | Yes (JTAG) | Yes (JTAG) |
Wichtigste Unterscheidungsmerkmale
- Fastest speed grade in the 84-PLCC MAX 7128 family (vs. EPM7128SLC84-10)
- Lead-free (Pb-free) finish on the same 84-PLCC footprint (vs. EPM7128SLC84-6)
- 68 user I/Os in a socketed 84-PLCC package (vs. EPM7096LC84-15)
Designhinweise
The EPM7128SLC84-6N requires a stable 5V supply on both VCCINT (core) and VCCIO (I/O bank) pins, with multiple VCC/GND pins distributed around the 84-PLCC package to minimize internal ground-bounce. Decouple each VCC pin with a 0.1uF ceramic capacitor placed as close to the package as possible, and add a single bulk 10-47uF tantalum or aluminum-polymer capacitor near the supply entry. During in-system programming via JTAG, Icc may rise 20-40% above steady-state, so the regulator headroom should accommodate transient peaks without sagging below 4.75V.
For 84-PLCC layouts, place the device in a socketed footprint if field replacement is anticipated (typical for legacy industrial and test-instrument designs). Route JTAG signals (TDI, TMS, TCK, TDO) as a short daisy-chain with 10K pull-ups on TDI/TMS/TCK; place the JTAG header within 50mm of the device to avoid noise coupling. For high-speed signals (>50 MHz) crossing PLCC pin fields, use ground traces between signal pins and minimize via stubs on the package break-out layer.
Do not directly interface 3.3V CMOS logic to EPM7128SLC84-6N 5V I/O pins - the VIH minimum (3.5V typical) may not be reached reliably by 3.3V outputs, and 5V input levels exceed the absolute-maximum ratings of 3.3V-only devices when driven in reverse. Use a level shifter (74LVC245, TXS0108E, or discrete MOSFET circuit) for mixed-voltage designs. Also note that the device is in last-time-buy status as of 2026 - new designs should target MAX II (EPM240) or MAX V (5M40ZE64) equivalents, which offer 3.3V/2.5V tolerant I/Os in smaller packages.
Estimated: At maximum toggle activity (all 68 I/Os switching at 100 MHz, 5V supply, worst-case 25 pF loads), the EPM7128SLC84-6N 84-PLCC dissipates approximately 1.2W steady-state. The PLCC package has theta_JA of ~40 C/W in still air, yielding a 48C junction rise above ambient at full activity. For enclosed industrial enclosures with limited airflow, derate activity or attach a small clip-on heatsink. Most glue-logic designs run at 5-15 MHz with 20-30 active I/Os, keeping dissipation well below 0.5W - no heatsink is required in typical use.
Compliance-Informationen
Per Arrow product page, the part is reported EU RoHS compliant in some listings but the legacy 5V MAX 7000S family is generally not Pb-free across all variants; the 'N' suffix indicates lead-free solder-ball/finish composition. AEC-Q100 not applicable (industrial/commercial logic IC, not automotive-qualified).
