EPM7128SLC84-6N vs EPM7128SLI84-10N Vergleich
Detaillierter Direktvergleich von EPM7128SLC84-6N von Intel und EPM7128SLI84-10N von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Intel
EPM7128SLC84-6N - MAX 7000S CPLD, 128 Macro, 6ns, 84-PLCC | Intel
EPM7128SLC84-6N ⚠ Letzte BestellmöglichkeitAltera
EPM7128SLI84-10N - MAX 7000S CPLD 128 Macro 10ns 84-PLCC | Intel / Altera
EPM7128SLI84-10N NrndSpezifikationsvergleich
| Parameter | EPM7128SLC84-6N | EPM7128SLI84-10N |
|---|---|---|
| Marke | Intel | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Letzte Kaufgelegenheit | NRND |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $8,75 | $8,45 |
| Family | MAX 7000S | MAX 7000S |
| Device System Gates | 2500 | — |
| Number of Macro Cells | 128 | — |
| Number of User I/Os | 68 | — |
| Number of Logic Blocks/Elements | 8 | — |
| Number of Global Clocks | 2 | — |
| Product Terms per Macro Cell | 32 | — |
| Maximum Operating Frequency | 147.1 MHz | — |
| Pin-to-Pin Delay (Speed Grade) | 6 ns | — |
| Versorgungsspannung | 5 V | — |
| Process Technology | CMOS, EEPROM | CMOS EEPROM |
| Program Memory Type | EEPROM | — |
| In-System Programmability | Yes (ISP via JTAG) | — |
| Gehäuse | 84-pin PLCC (J-lead) | 84-pin PLCC (J-Lead) |
| Betriebstemperatur | [DATA_NEEDED: operating temperature range] | -40 C to +85 C (Industrial) |
| RoHS-Status | Non-Compliant (legacy 5V part) | [DATA_NEEDED: RoHS compliance per latest Intel/Altera declaration] |
| Logic Cells / Macro Cells | — | 128 macro cells |
| Usable Gates | — | 2,500 |
| Number of Logic Elements / Blocks | — | 16 Logic Array Blocks (LABs) |
| User I/Os | — | 68 |
| Propagation Delay (tPD) | — | 10 ns |
| Maximum Frequency (fMAX) | — | 125 MHz |
| Supply Voltage (VCCINT) | — | 4.75 V to 5.25 V (5 V typical) |
| I/O Voltage Tolerance | — | 3.3 V / 5 V MultiVolt I/O |
| Programmability | — | In-system programmable (ISP), non-volatile EEPROM |
| Boundary-Scan (JTAG) | — | IEEE Std 1149.1 compliant |
| Montageart | — | Surface Mount |
| Lead-Free | — | [DATA_NEEDED: lead-free per latest Intel/Altera declaration] |