HI5767/2IA - 10-Bit 40 MSPS ADC, Pipelined | Renesas
Teilenummer: HI5767/2IA ✓ Aktiv| Menge | Stückpreis | Gesamt |
|---|---|---|
| 1 | $12.5 | $12,50 |
| 10 | $11.25 | $112,50 |
| 100 | $9.8 | $980,00 |
| 500 | $8.6 | $4.300,00 |
| 1.000 | $7.45 | $7.450,00 |
HI5767/2IA Übersicht
An ADC (analog-to-digital converter) is a data-conversion component that translates a continuous-time analog signal into a discrete digital codeword at a defined sample rate. The HI5767 belongs to the pipelined-ADC hypernymy: pipelined ADC -> Nyquist-rate ADC -> ADC -> data converter -> mixed-signal IC. Within a system hierarchy it sits between the analog front end (amplifiers, filters, muxes) and the digital signal processor, FPGA, or ASIC that consumes the samples.
Key features of the HI5767/2IA include 10-bit resolution with no missing codes, an internal 2.5 V bandgap reference (with REF pin for external drive), single +5 V analog supply operation, and TTL/CMOS-compatible digital outputs. The differential input structure accepts single-ended or differential drive, and the wide input bandwidth supports undersampling IF applications. The pipelined architecture delivers sub-channel latency with low aperture jitter, making the part well suited to multi-channel time-interleaved systems where each ADC sees one phase of the sampling clock.
Typical use cases include medical imaging front ends, communications IF digitization, CCD/CIS scanner signal chains, and video acquisition. The 28-SSOP footprint and +5 V-only supply simplify retrofit into legacy 5 V designs and reduce BOM cost versus LVDS-interface ADCs. Industrial-grade temperature rating plus a CMOS process make the part appropriate for cost-sensitive high-volume embedded products.
When designing in this ADC, use a low-impedance analog input driver with sufficient bandwidth, keep analog/digital grounds separate, and place a 0.1 uF decoupling cap close to each supply pin. The internal reference can be bypassed with an external 2.5 V reference if system calibration demands tighter drift.
Drop-in-Alternativen für HI5767/2IA – gleiches Gehäuse, Pin-kompatibel. Bauteile mit anderem Gehäuse, die eine PCB-Überarbeitung erfordern, sind ausgeschlossen.
Varianten dieser Serie
Modelle derselben Serie, die drop-in-kompatibel sind mit HI5767/2IA (gleiche Bauform und Footprint) – abweichend in Architecture, Operating Temperature, Package, Resolution, RoHS Status.
Schnellvergleichstool – Wählen Sie Alternativbauteile für den Direktvergleich:
HI5767/1IA
✅ Drop-In📋 Referenzalternative (nicht im Katalog)
HI5767/3IA
✅ Drop-In📋 Referenzalternative (nicht im Katalog)
HI5767/2IAZ
✅ Drop-In✓ Auf Lager
$4.65 / Stück
Datenblatt ansehen →HI5767/2IA-10
✅ Drop-In📋 Referenzalternative (nicht im Katalog)
AD9220ARZ
✅ Drop-In📋 Referenzalternative (nicht im Katalog)
HI5767/2IA Grenzwerte & elektrische Eigenschaften
| Auflösung | 10 bit |
| Sample Rate (this grade) | 40 MSPS |
| Family Sample Rates | 20 (/1), 40 (/2), 60 (/3) MSPS |
| Architecture | Pipelined, fully differential |
| Analog Input | Differential or single-ended |
| Analog Supply | +5 V (single) |
| Digital Supply | +5 V or +3 V (TTL/CMOS outputs) |
| Internal Reference | 2.5 V bandgap (REF pin accessible) |
| Betriebstemperatur | -40 C to +85 C (industrial) |
| Gehäuse | 28-pin SSOP (3.90 mm width) |
| Montageart | Surface Mount |
| Process Technology | CMOS |
| RoHS-Status | Compliant |
HI5767/2IA Pin-Konfiguration
| Pin 1 | AVDD — Analog +5 V supply |
| Pin 2 | AGND — Analog ground |
| Pin 3 | AIN+ — Differential analog input (non-inverting) |
| Pin 4 | AIN- — Differential analog input (inverting) |
| Pin 5 | AGND — Analog ground |
| Pin 6 | REF — Internal 2.5 V bandgap reference (bypass or external drive) |
| Pin 7 | REFSENSE — Reference ground sense |
| Pin 8 | AGND — Analog ground |
| Pin 9 | DRVDD — Digital output driver supply (+5 V or +3 V) |
| Pin 10 | DVDD — Digital core supply |
| Pin 11 | D0 — Digital output bit 0 (LSB) |
| Pin 12 | D1 — Digital output bit 1 |
| Pin 13 | D2 — Digital output bit 2 |
| Pin 14 | D3 — Digital output bit 3 |
| Pin 15 | D4 — Digital output bit 4 |
| Pin 16 | D5 — Digital output bit 5 |
| Pin 17 | D6 — Digital output bit 6 |
| Pin 18 | D7 — Digital output bit 7 |
| Pin 19 | D8 — Digital output bit 8 |
| Pin 20 | D9 — Digital output bit 9 (MSB) |
| Pin 21 | DRVDD — Digital output driver supply (second pin) |
| Pin 22 | DGND — Digital ground |
| Pin 23 | DGND — Digital ground |
| Pin 24 | OTR — Out-of-range indicator |
| Pin 25 | NC — Not connected |
| Pin 26 | NC — Not connected |
| Pin 27 | CLK — Sample clock input |
| Pin 28 | CLK- — Complementary sample clock (or GND for single-ended clock) |
Typische Anwendungen
HI5767/2IA ist geeignet für 6 Anwendungs: Medical Imaging Front End, Communications IF Digitization, CCD/CIS Scanner Signal Chain, Video Acquisition Boards, Industrial Test & Measurement, Set-Top Box / DVB Downconverter.
Medical Imaging Front End
The HI5767/2IA fits medical imaging front ends thanks to its 40 MSPS sample rate, 10-bit resolution, and differential analog input that accepts direct drive from a low-noise imaging pre-amplifier. Placed between the sensor analog front end (e.g., photodiode or ultrasound transducer + LNA) and the FPGA image-processing pipeline, the ADC samples the conditioned waveform into a digital stream. Unlike higher-resolution 12-14 bit ADCs that sacrifice speed, the HI5767/2IA balances 10 bits with 40 MSPS - sufficient dynamic range for ultrasound beamforming and intermediate frame rates. The 28-SSOP footprint simplifies retrofit into legacy 5 V medical instrumentation boards.
Empfohlen
Communications IF Digitization
The HI5767/2IA is well matched to communications IF digitization because its wide input bandwidth supports undersampling of IF carriers in the 20-30 MHz range, while the 40 MSPS Nyquist rate cleanly captures baseband I/Q streams. Placed after the mixer and anti-alias LPF, the ADC delivers 10-bit I/Q words directly to the baseband DSP or FPGA. Compared with an LVDS-output ADC, the HI5767/2IA's TTL/CMOS outputs simplify direct connection to 5 V FPGAs and ASICs without level shifters. The differential pipelined architecture keeps aperture jitter low for clean EVM in narrow-band receivers.
Empfohlen
CCD/CIS Scanner Signal Chain
The HI5767/2IA suits CCD and CIS (contact image sensor) scanner analog front ends where pixel rates of 20-40 MHz are common in mid-resolution document scanners. Positioned after the correlated double-sampler (CDS) and programmable gain amplifier (PGA), the ADC converts each pixel into a 10-bit codeword at the line scan rate. The internal 2.5 V reference can be trimmed or replaced with an external reference for calibrated color accuracy across the scanner's lifetime. Its industrial -40 C to +85 C temperature rating supports the rugged thermal environment of high-throughput scanner modules.
Empfohlen
Video Acquisition Boards
The HI5767/2IA supports SD and intermediate-rate video acquisition boards because its 40 MSPS sample rate far exceeds the 27 MHz required by ITU-R BT.601 digital video, leaving comfortable headroom for oversampling. Positioned between the video amp/clamper and the FPGA frame-grabber, the ADC delivers 10-bit 4:2:2 or 4:4:4 component video directly into digital processing. The single +5 V supply and TTL/CMOS outputs simplify board design versus LVDS-interface ADCs, reducing BOM cost in volume security, broadcast, and industrial video products.
Empfohlen
Industrial Test & Measurement
The HI5767/2IA is a natural fit for bench-top and rack-mount test & measurement instruments such as digital oscilloscopes, spectrum analyzer IF strips, and transient recorders. Its 40 MSPS rate, 10-bit resolution, and differential input preserve signal integrity across a wide analog bandwidth, while the 28-SSOP industrial-rated package handles the thermal demands of densely populated chassis. Placed after the front-end attenuator/amplifier and anti-alias filter, the ADC streams data into an FPGA or DSP for FFT, peak detect, or waveform capture.
Empfohlen
Set-Top Box / DVB Downconverter
The HI5767/2IA fits DVB and ATSC tuner/demodulator modules where a 10-bit ADC digitizes the IF output of the downconversion stage for the demodulator DSP. The 40 MSPS rate comfortably covers 36-44 MHz IF sampling, while the differential input rejects common-mode noise from the tuner chain. Positioned after the SAW IF filter and AGC amplifier, the ADC delivers baseband samples directly into the demodulator. Compared with integrated tuner+ADC solutions, the HI5767/2IA paired with a discrete front end gives designers more flexibility in receiver architecture.
Empfohlen
Zusammenfassung der empfohlenen Produkte
Technische Referenzdaten für HI5767/2IA – Vergleich, Designhinweise und Compliance-Informationen.
Auswahlhilfe
Vergleich mit Alternativen
| Parameter | Dieses Produkt | HI5767/1IA | HI5767/3IA | HI5767/2IAZ | HI5767/2IA-10 | AD9220ARZ |
|---|---|---|---|---|---|---|
| Brand | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics | Analog Devices |
| Package | 28-SSOP (3.90 mm) | 28-SSOP (3.90 mm) - same | 28-SSOP (3.90 mm) - same | 28-SSOP (3.90 mm) - same | 28-SSOP (3.90 mm) - same | 28-SSOP - same |
| Resolution | 10 bit | 10 bit | 10 bit | 10 bit | 10 bit | 12 bit |
| Sample Rate | 40 MSPS | 20 MSPS | 60 MSPS | 40 MSPS | 40 MSPS | 10 MSPS |
| Architecture | Pipelined | Pipelined | Pipelined | Pipelined | Pipelined | Pipelined |
| Analog Supply | +5 V | +5 V | +5 V | +5 V | +5 V | +5 V |
| Input Type | Differential | Differential | Differential | Differential | Differential | Differential |
| Internal Reference | Yes (2.5 V bandgap) | Yes (2.5 V bandgap) | Yes (2.5 V bandgap) | Yes (2.5 V bandgap) | Yes (2.5 V bandgap) | Yes (2.5 V bandgap) |
| Operating Temperature | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C |
Wichtigste Unterscheidungsmerkmale
- Single +5 V supply with TTL/CMOS outputs simplifies 5 V system integration (vs. AD9220ARZ)
- Industry-standard 28-SSOP package with full pinout compatibility across all speed grades (vs. HI5767/1IA and HI5767/3IA)
- Differential analog input with internal 2.5 V reference (vs. Single-ended ADCs of similar speed)
Designhinweise
Use a 4-layer PCB with a dedicated analog ground plane and a separate digital ground plane joined at a single point beneath the ADC. Place 0.1 uF ceramic decoupling caps as close as possible to AVDD and DRVDD pins, with a 10 uF bulk cap at the supply entry. Keep analog input traces symmetric and matched for the differential pair, and route clock traces away from analog inputs to minimize digital feedthrough.
Drive the CLK pin with a low-jitter clock source (< 5 ps RMS) to preserve SNR and ENOB at the 40 MSPS Nyquist frequency. If the application uses a single-ended clock, tie CLK- to ground; otherwise drive differentially for best aperture-jitter performance. Add a series termination resistor near the clock driver to dampen reflections, and keep the clock trace length matched to within 1 mm.
Do not leave the REF pin floating - either bypass it with the recommended capacitor network (per datasheet) or drive with an external 2.5 V reference for tighter absolute accuracy. Avoid driving AIN+ and AIN- asymmetrically; the differential input structure assumes matched common-mode voltage. Finally, ensure analog input common-mode stays within the datasheet range; violations cause severe distortion and may damage the input ESD structures.
Compliance-Informationen
RoHS compliance per Renesas product page. Industrial -40 C to +85 C temperature rating but no AEC-Q100 automotive qualification. The HI5767/2IAZ variant adds lead-free / RoHS packaging.
