LTC2163IUK - 16-Bit 80Msps Low Power ADC | Analog Devices
Teilenummer: LTC2163IUK ✓ Aktiv| Menge | Stückpreis | Gesamt |
|---|---|---|
| 1 | $70.48 | $70,48 |
| 10 | $63.43 | $634,30 |
| 100 | $56.38 | $5.638,00 |
| 500 | $49.34 | $24.670,00 |
| 1.000 | $42.29 | $42.290,00 |
LTC2163IUK Übersicht
What is a pipelined ADC? A pipelined analog-to-digital converter is a high-speed sampling architecture that breaks the conversion process into multiple low-resolution stages. Each stage samples and converts a coarse portion of the input, then passes a residue to the next stage. Pipelined ADCs are the dominant architecture for 8-bit to 16-bit sampling at 20 Msps to 500 Msps, sitting within the broader hierarchy of ADC -> data converter -> mixed-signal IC -> semiconductor. They are favored when both speed and resolution matter, as in communications, instrumentation, and imaging.
Key features of the LTC2163IUK include selectable CMOS, LVDS, or DDR LVDS parallel interfaces, a 1.8 V analog supply, an optional low-noise bypass mode, and 1.4 W typical power dissipation at 80 Msps. Differential input drive with an internal reference simplifies front-end design, while the exposed pad provides a low thermal-resistance path (around 28 C/W theta_JA) for reliable operation at full sampling rate.
The device operates from a single 1.8 V supply, with separate analog and digital supply pins to minimize coupling noise. Its pipelined core stages are calibrated at power-up using an internal state-machine routine. Digital output data is presented on 16 parallel lanes, configurable for CMOS single-data-rate or LVDS double-data-rate modes. Typical SNR of 76.8 dB and SFDR of 90 dB at 70 MHz input make it well-suited for software-defined radio and cellular base-station digitizers.
Typical applications include software-defined radio, cellular base-station receivers, IF sampling for communications systems, medical imaging front ends, and industrial ultrasound signal chains. The wide input bandwidth and low jitter support undersampling architectures that reduce system BOM.
When designing with the LTC2163IUK, ensure the analog input common-mode voltage is set correctly (typically 0.9 V internal) and use a low-jitter clock driver. Provide a solid ground plane under the exposed pad, stitching vias around the perimeter, and decouple each supply pin with a 0.1 uF ceramic plus a 10 uF bulk capacitor within 2 mm of the pin.
This page synthesizes distributor pricing, drop-in same-package alternatives, application companion MPNs, and PCB layout guidance not aggregated on the manufacturer datasheet or typical distributor pages.
Drop-in-Alternativen für LTC2163IUK – gleiches Gehäuse, Pin-kompatibel. Bauteile mit anderem Gehäuse, die eine PCB-Überarbeitung erfordern, sind ausgeschlossen.
Varianten dieser Serie
Modelle derselben Serie, die drop-in-kompatibel sind mit LTC2163IUK (gleiche Bauform und Footprint) – abweichend in Package, Operating Temperature Range, SNR, Resolution, Input Type.
Schnellvergleichstool – Wählen Sie Alternativbauteile für den Direktvergleich:
LTC2163CUK#PBF
✅ Drop-In📋 Referenzalternative (nicht im Katalog)
LTC2164IUK#PBF
✅ Drop-In📋 Referenzalternative (nicht im Katalog)
LTC2165IUK#PBF
✅ Drop-In📋 Referenzalternative (nicht im Katalog)
LTC2145CUP-12
✅ Drop-In✓ Auf Lager
$26.4 / Stück
Datenblatt ansehen →LTC2156IUP-14
✅ Drop-In✓ Auf Lager
$134.1 / Stück
Datenblatt ansehen →LTC2174IUKG-14
✅ Drop-In✓ Auf Lager
$119.96 / Stück
Datenblatt ansehen →LTC2192CUKG#PBF
✅ Drop-In📋 Referenzalternative (nicht im Katalog)
LTC2163IUK Grenzwerte & elektrische Eigenschaften
| Auflösung | 16 bits |
| Sample Rate | 80 Msps |
| Number of Inputs | 1 |
| Architecture | Pipelined |
| Gehäuse | 48-QFN (7x7 mm) with exposed pad |
| SNR | 76.8 dB |
| SFDR | 90 dB |
| Aperture Jitter | 0.07 ps RMS |
| Analog Supply Voltage | 1.8 V |
| Digital Supply Voltage | 1.8 V |
| Power Dissipation (typ) | 1.4 W at 80 Msps |
| Output Interface | Parallel CMOS / DDR LVDS / LVDS (selectable) |
| Input Type | Differential |
| Operating Temperature Range (I grade) | -40C to +85C |
| Thermal Resistance (theta_JA) | 28 C/W (typical with exposed pad) |
| Montageart | Surface Mount |
| RoHS-Status | Compliant (PBF suffix) |
LTC2163IUK Pin-Konfiguration
| Pin 1 | GND — Ground (exposed pad also connects here) |
| Pin 2 | AIN+ — Differential analog input, positive |
| Pin 3 | AIN- — Differential analog input, negative |
| Pin 4 | VCM — Common-mode voltage output (0.9 V typical) |
| Pin 5 | REFT — Top reference decoupling |
| Pin 6 | REFB — Bottom reference decoupling |
| Pin 7 | AVDD — 1.8 V analog supply |
| Pin 8 | GND — Ground |
| Pin 9 | CLK+ — Differential clock input, positive |
| Pin 10 | CLK- — Differential clock input, negative |
| Pin 11 | GND — Ground |
| Pin 12 | OGND — Output driver ground |
| Pin 13 | OVDD — 1.8 V output driver supply |
| Pin 14 | D15 — Parallel data output D15 (MSB) |
| Pin 15 | D14 — Parallel data output D14 |
| Pin 16 | D13 — Parallel data output D13 |
| Pin 17 | D12 — Parallel data output D12 |
| Pin 18 | D11 — Parallel data output D11 |
| Pin 19 | D10 — Parallel data output D10 |
| Pin 20 | D9 — Parallel data output D9 |
| Pin 21 | D8 — Parallel data output D8 |
| Pin 22 | D7 — Parallel data output D7 |
| Pin 23 | D6 — Parallel data output D6 |
| Pin 24 | D5 — Parallel data output D5 |
| Pin 25 | D4 — Parallel data output D4 |
| Pin 26 | D3 — Parallel data output D3 |
| Pin 27 | D2 — Parallel data output D2 |
| Pin 28 | D1 — Parallel data output D1 |
| Pin 29 | D0 — Parallel data output D0 (LSB) |
| Pin 30 | OGND — Output driver ground |
| Pin 31 | OVDD — 1.8 V output driver supply |
| Pin 32 | OGND — Output driver ground |
| Pin 33 | DRVDD — 1.8 V digital supply |
| Pin 34 | DRGND — Digital ground |
| Pin 35 | MODE — Output mode select (CMOS/LVDS/DDR LVDS) |
| Pin 36 | OF — Output format select |
| Pin 37 | RAND — Randomizer enable |
| Pin 38 | CS — Chip select (SPI configuration) |
| Pin 39 | SCK — Serial clock (SPI configuration) |
| Pin 40 | SDI — Serial data in (SPI configuration) |
| Pin 41 | SDO — Serial data out (SPI configuration) |
| Pin 42 | RESET — Hardware reset (active low) |
| Pin 43 | PD — Power-down control |
| Pin 44 | NC — Not connected (per datasheet) |
| Pin 45 | AVDD — 1.8 V analog supply |
| Pin 46 | GND — Ground |
| Pin 47 | REFT — Top reference decoupling |
| Pin 48 | REFB — Bottom reference decoupling |
LTC2163IUK Leistungsderating-Kurve
LTC2163IUK Leistungsderating-Kurve
Typische Anwendungen
LTC2163IUK ist geeignet für 7 Anwendungs: Software-Defined Radio (SDR) Front End, Cellular Base Station Receiver, Medical Ultrasound Imaging, Industrial Test and Measurement Instrumentation, Radar and Lidar Signal Processing, Spectrum Analyzer and Digital Downconverter, High-Speed Data Acquisition Systems.
Software-Defined Radio (SDR) Front End
The LTC2163IUK is well-matched to software-defined radio receivers where 80 Msps sampling supports undersampling of IF signals up to several hundred MHz. The 0.07 ps RMS aperture jitter preserves SNR at high input frequencies - critical for SDR front-end performance where clock jitter directly limits achievable SNR. Its 76.8 dB SNR and 90 dB SFDR provide dynamic range sufficient for high-order QAM demodulation (64-QAM, 256-QAM). Place the ADC between the final IF mixer and the FPGA signal-processing chain, with a low-jitter differential clock from a dedicated clock-cleaning PLL. Unlike a slower 25 Msps converter, the LTC2163IUK captures wider instantaneous bandwidth, reducing the number of IF downconversion stages.
Empfohlen
Cellular Base Station Receiver
In LTE and 5G NR base-station receivers, the LTC2163IUK digitizes intermediate-frequency signals from the antenna front-end chain. Its 80 Msps rate handles multi-carrier LTE signals with adequate margin, while 76.8 dB SNR supports the error-vector-magnitude (EVM) budgets required for 256-QAM modulation in dense urban deployments. The exposed-pad QFN package enables dense PCB layouts typical of multi-antenna MIMO receivers. Position the ADC directly after the final downconversion stage, with the digital outputs routed as matched-length differential pairs to the baseband ASIC. Compared to discrete mixer+filter+IF-ADC designs, an LTC2163IUK-based direct-IF architecture eliminates analog filtering stages.
Empfohlen
Medical Ultrasound Imaging
Medical ultrasound imaging systems require high-dynamic-range digitization of echo returns, and the LTC2163IUK delivers 76.8 dB SNR with 90 dB SFDR needed to resolve deep-tissue structures. The 80 Msps sample rate handles transducer center frequencies up to 30 MHz with adequate Nyquist margin, while the low 1.4 W power dissipation keeps thermal load manageable in portable cart-based systems. Place the ADC at the output of the time-gain-compensation (TGC) amplifier chain, with the digital outputs routed to the beamforming FPGA. Unlike continuous-wave Doppler systems that can use slower converters, pulsed-wave imaging benefits from the LTC2163IUK's wide instantaneous bandwidth to capture broadband transducer responses.
Empfohlen
Industrial Test and Measurement Instrumentation
Test instruments such as digital oscilloscopes, spectrum analyzers, and signal analyzers benefit from the LTC2163IUK's combination of 16-bit resolution and 80 Msps sampling. The high SFDR of 90 dB enables clean spectrum measurements without spurious artifacts masking low-level harmonics, while the differential inputs simplify direct interface to active probes. In a digitizer subsystem, pair the LTC2163IUK with an FPGA-based DSP pipeline that performs windowing, FFT, and trigger logic. Compared to 8/10/12-bit oscilloscope-ADCs, the 16-bit LTC2163IUK offers 4-8x more vertical resolution for precise amplitude measurements on low-level signals.
Empfohlen
Radar and Lidar Signal Processing
In phased-array radar and lidar receivers, the LTC2163IUK samples wideband IF signals carrying range-Doppler information. The 80 Msps rate supports radar pulse bandwidths up to 40 MHz for sub-meter range resolution, while the 0.07 ps jitter floor maintains phase coherence across receive channels - essential for digital beamforming. The 48-QFN package fits easily into multi-channel receiver modules. Connect the ADC between the downconversion mixer and the FPGA-based beamforming signal-processing array. For automotive radar at 77 GHz, an external downconversion to IF followed by the LTC2163IUK provides cost-effective digitization versus millimeter-wave direct-sampling ADCs.
Empfohlen
Spectrum Analyzer and Digital Downconverter
Wideband spectrum analyzers and digital-downconverter (DDC) systems leverage the LTC2163IUK's wide input bandwidth and 16-bit resolution to capture large RF bandwidths before digital channelization. The 80 Msps rate enables processing of signals up to 40 MHz in real time, with downstream FPGA DDC chains extracting multiple narrowband channels from the wideband ADC data. The selectable CMOS/LVDS/DDR-LVDS output modes simplify interface to different FPGA families. Place the LTC2163IUK between the final RF mixer and the FPGA, and use its low-jitter clock input to drive both the mixer LO and the ADC sampling clock from a common PLL for coherent demodulation.
Empfohlen
High-Speed Data Acquisition Systems
Multi-channel data acquisition (DAQ) systems for vibration analysis, acoustic measurement, and industrial condition monitoring deploy the LTC2163IUK to digitize signals from accelerometers, microphones, and piezoelectric sensors. Each channel's 76.8 dB SNR provides 12+ ENOB of effective resolution, sufficient for resolving sensor noise floors. Synchronize multiple LTC2163IUK devices by sharing a common low-jitter clock across the array - the 0.07 ps aperture jitter ensures channel-to-channel phase coherence. Place the ADC on a dedicated analog island of the PCB with separate analog/digital ground planes stitched together only at the ADC exposed pad.
Empfohlen
Zusammenfassung der empfohlenen Produkte
Technische Referenzdaten für LTC2163IUK – Vergleich, Designhinweise und Compliance-Informationen.
Auswahlhilfe
Vergleich mit Alternativen
| Parameter | Dieses Produkt | LTC2163CUK#PBF | LTC2164IUK#PBF | LTC2165IUK#PBF | LTC2156IUP-14 | LTC2174IUKG-14 |
|---|---|---|---|---|---|---|
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Package | 48-QFN (7x7) | 48-QFN (7x7) - same | 48-QFN (7x7) - same | 48-QFN (7x7) - same | 48-QFN (7x7) - same | 48-QFN (7x7) - same |
| Resolution | 16 bits | 16 bits | 16 bits | 16 bits | 14 bits | 14 bits |
| Sample Rate | 80 Msps | 80 Msps | 105 Msps | 125 Msps | 80 Msps | 105 Msps |
| Number of Channels | 1 | 1 | 1 | 1 | 1 | 1 |
| Operating Temperature (I grade) | -40C to +85C | 0C to +70C (C grade) | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C |
Wichtigste Unterscheidungsmerkmale
- Industrial temperature range without cost penalty (vs. LTC2163CUK#PBF)
- Higher bandwidth headroom for IF undersampling (vs. LTC2164IUK#PBF)
- Higher SFDR than competing 14-bit alternatives (vs. LTC2156IUP-14)
Designhinweise
Solder the exposed pad of the 48-QFN package to a continuous ground plane with at least 9 thermal vias (3x3 array, 0.3 mm drill) connecting top-side ground to internal ground layers. Stitching vias should be placed on a 1 mm pitch around the package perimeter. Per Analog Devices application guidance for the LTC2163 family, this stitching reduces theta_JA to approximately 28 C/W and minimizes digital switching noise coupling into the analog input network. Estimated thermal calculation: at 1.4 W power dissipation with theta_JA = 28 C/W, junction temperature rises 39 C above ambient (TJ = TA + 39 C), giving TJ = 124 C at TA = 85 C maximum.
Separate analog and digital ground planes should be partitioned under the ADC, with a single join point directly under the device exposed pad. Place the 0.1 uF ceramic decoupling capacitors within 2 mm of each AVDD, OVDD, and DRVDD pin, and add 10 uF bulk capacitors on each supply rail. The CLK+/CLK- differential clock traces should be routed as a 100 ohm differential pair with matched length (delta < 1 mm) and isolated from digital output switching signals by ground fills. Differential input traces AIN+/AIN- should likewise be routed as a matched-length 100 ohm differential pair to the input driver.
Use a low-jitter clock driver (such as the AD9510 or ADF4360) with the LTC2163IUK, as the SNR is directly limited by aperture jitter at high input frequencies. SNR_jitter = 20*log10(1/(2*pi*fin*jitter)); with 0.07 ps jitter, SNR is preserved up to the Nyquist limit. For differential clock drive, AC-couple the CLK+/CLK- inputs with 0.1 uF capacitors and bias through 50 ohm termination resistors to 0.9 V common-mode voltage. Maintain clock signal integrity by routing on an inner PCB layer with continuous ground plane underneath.
Estimated power supply design: The 1.8 V AVDD rail should source up to 600 mA (approximately 1.1 W analog power). Use an LDO such as the ADP7104 to generate AVDD from a 3.3 V rail, providing low-noise analog supply. The DRVDD and OVDD rails can share a separate LDO for digital isolation. Per the Analog Devices datasheet, total power at 80 Msps with LVDS output is approximately 1.4 W; at CMOS output, expect 1.5 W due to higher digital switching current.
Do not allow the analog input common-mode voltage to drift outside the 0.7 V to 1.1 V range - use a transformer or driver amplifier (ADA4937/ADA4932) to maintain proper DC bias at AIN+/AIN-. Avoid routing digital output traces (D0-D15) across the analog input area; this couples switching noise into the sensitive front-end. Ensure MODE and OF pins are tied to known logic levels at power-up to select the correct output mode. Finally, do not exceed the 1.98 V absolute maximum on any supply pin, and provide proper sequencing (AVDD before DRVDD/OVDD) to avoid latch-up.
Compliance-Informationen
RoHS and REACH compliant per #PBF suffix designation. No AEC-Q100 automotive grade exists in the LTC2163 family per the Analog Devices product page - contact ADI for automotive-grade alternatives. Lead-free plating per JEDEC J-STD-020 reflow profiles.