MAX1165AEUI+ - 16-Bit Low-Power SAR ADC | Maxim Integrated
Teilenummer: MAX1165AEUI+ ✓ Aktiv| Menge | Stückpreis | Gesamt |
|---|---|---|
| 1 | $12.45 | $12,45 |
| 10 | $11.21 | $112,10 |
| 100 | $9.95 | $995,00 |
| 500 | $8.92 | $4.460,00 |
| 1.000 | $7.95 | $7.950,00 |
MAX1165AEUI+ Übersicht
A SAR ADC (Successive Approximation Register Analog-to-Digital Converter) is a type of data converter that resolves each conversion in a fixed number of clock cycles by successively comparing the sampled input against an internal binary-weighted capacitor DAC. SAR ADCs sit between flash and delta-sigma converters in the speed/resolution hierarchy: faster than delta-sigma at moderate resolution, much lower power than flash, and inherently free of pipeline latency. They are widely used in industrial process control, instrumentation, and data-acquisition front-ends where one conversion per sample is required.
Key features of the MAX1165AEUI+ include ±1 LSB DNL (no missing codes), an internal 4.096V bandgap reference with the option to use an external reference, a hardware RDY/INT output, and an SPI-/QSPI-/MICROWIRE-compatible serial-mode option (selected at power-up via the INT/EOC pin). The reference architecture lets designers trade absolute accuracy against input range, and the internal oscillator eliminates the need for an external clock in many systems. The 28-TSSOP footprint makes it PCB-friendly for both hand prototyping and high-density acquisition modules.
The MAX1165AEUI+ uses a charge-redistribution DAC with input T/H and auto-calibration on every conversion, giving excellent AC and DC performance across temperature. Power-down between conversions reduces supply current to under 1 mA in idle, making the device attractive for battery-backed instrumentation. The parallel interface allows direct connection to microcontrollers and DSPs without serial glue logic, and the asynchronous RDY signal simplifies interrupt-driven sampling.
Typical applications include multi-channel PLC analog input modules, weigh-scale front-ends, transducer signal conditioning, and portable data loggers. The wide ±10V true-differential input range eliminates external signal-conditioning op-amps in many 4-20 mA-style loops, and the 165 ksps rate is sufficient for vibration analysis and motor-control current sensing. Designers commonly pair it with a precision op-amp buffer (MAX4475) and an isolated DC/DC to build complete 16-bit acquisition channels.
When designing with the MAX1165AEUI+, ensure the analog and digital supplies are decoupled with separate 0.1 µF ceramic capacitors placed close to the AVCC and DVCC pins. The REF pin requires a 4.7 µF ceramic or tantalum bypass cap to meet the 100 dB SINAD specification; a smaller capacitor will degrade noise performance. Always read the RDY/INT pin via level-triggered interrupts rather than polling to avoid missed conversions at the full 165 ksps rate.
This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet — including same-brand family members like MAX1165ACUI+ and cross-brand pin-compatible ADCs from Analog Devices and TI.
Drop-in-Alternativen für MAX1165AEUI+ – gleiches Gehäuse, Pin-kompatibel. Bauteile mit anderem Gehäuse, die eine PCB-Überarbeitung erfordern, sind ausgeschlossen.
Varianten dieser Serie
Modelle derselben Serie, die drop-in-kompatibel sind mit MAX1165AEUI+ (gleiche Bauform und Footprint) – abweichend in Operating Temperature, Package, MSL Level, RoHS Status, Resolution.
Schnellvergleichstool – Wählen Sie Alternativbauteile für den Direktvergleich:
MAX1165ACUI+
✅ Drop-In✓ Auf Lager
$6.1 / Stück
Datenblatt ansehen →MAX1165BEUI+
✅ Drop-In ⚠️ Spezifikationen ungeprüft✓ Auf Lager
$9.57 / Stück
Datenblatt ansehen →MAX1166BEUI+
✅ Drop-In ⚠️ Spezifikationen ungeprüft📋 Referenzalternative (nicht im Katalog)
MAX1166AEUI+
✅ Drop-In ⚠️ Spezifikationen ungeprüft📋 Referenzalternative (nicht im Katalog)
MAX1156AEUP+T
✅ Drop-In ⚠️ Spezifikationen ungeprüft✓ Auf Lager
$7.8 / Stück
Datenblatt ansehen →MAX1165AEUI+ Grenzwerte & elektrische Eigenschaften
| Auflösung | 16 bit |
| Architecture | SAR (Successive Approximation) |
| Input Channels | 1 (true differential) |
| Eingangsspannungsbereich | ±10 V (differential, MAX1165) |
| Analog Supply Voltage | 4.75 V to 5.25 V |
| Digital Supply Voltage | 2.7 V to 5.25 V |
| Throughput Rate | 165 ksps |
| INL (Max) | ±1 LSB |
| DNL (Max) | ±1 LSB |
| SINAD | 100 dB |
| Internal Reference | 4.096 V bandgap |
| Schnittstelle | Parallel (16-bit), serial-mode compatible |
| Betriebstemperatur | -40 °C to +85 °C (industrial) |
| Gehäuse | 28-pin TSSOP |
| Montageart | Surface Mount |
| MSL-Level | 1 (unlimited floor life at ≤30 °C/85% RH) |
| RoHS-Status | Compliant |
| Terminal Form | Gull Wing |
| Converter Type | ADC, single channel, SAR |
MAX1165AEUI+ Pin-Konfiguration
| Pin 1 | AIN+ — Positive analog input (true differential) |
| Pin 2 | AIN- — Negative analog input (true differential) |
| Pin 3 | REF — Internal 4.096 V reference / external reference input |
| Pin 4 | REFGND — Reference ground |
| Pin 5 | AVCC — Analog supply (4.75 V to 5.25 V) |
| Pin 6 | AGND — Analog ground |
| Pin 7 | CS — Chip select (active low) |
| Pin 8 | RD — Read strobe (active low) |
| Pin 9 | WR/RCLK — Write / conversion start (active low) |
| Pin 10 | INT/EOC — Interrupt / End-of-conversion (open drain) |
| Pin 11 | CLK — External clock input (or internal oscillator with cap to AGND) |
| Pin 12 | D15 — Parallel data bit 15 (MSB) |
| Pin 13 | D14 — Parallel data bit 14 |
| Pin 14 | D13 — Parallel data bit 13 |
| Pin 15 | D12 — Parallel data bit 12 |
| Pin 16 | D11 — Parallel data bit 11 |
| Pin 17 | D10 — Parallel data bit 10 |
| Pin 18 | D9 — Parallel data bit 9 |
| Pin 19 | D8 — Parallel data bit 8 |
| Pin 20 | D7 — Parallel data bit 7 |
| Pin 21 | D6 — Parallel data bit 6 |
| Pin 22 | D5 — Parallel data bit 5 |
| Pin 23 | D4 — Parallel data bit 4 |
| Pin 24 | D3 — Parallel data bit 3 |
| Pin 25 | D2 — Parallel data bit 2 |
| Pin 26 | D1 — Parallel data bit 1 |
| Pin 27 | D0 — Parallel data bit 0 (LSB) |
| Pin 28 | DVCC — Digital supply (2.7 V to 5.25 V) |
Typische Anwendungen
MAX1165AEUI+ ist geeignet für 6 Anwendungs: Industrial PLC Analog Input Module, Weigh-Scale and Load-Cell Front-End, Multi-Channel Data Acquisition Card, Portable Battery-Powered Data Logger, Medical Patient Monitoring Equipment, Motor Control Current Sensing.
Industrial PLC Analog Input Module
The MAX1165AEUI+ suits 16-bit industrial PLC analog input modules because of its ±10 V true-differential input range, which handles the ±24 V fault transients typical in 4-20 mA loops without external signal-conditioning op-amps. With 165 ksps throughput and ±1 LSB INL, it captures process variables (pressure, flow, temperature-via-RTD) at the loop's bandwidth limit. Place the part between a 250 Ω sense resistor and the MCU/DSP parallel bus; decoupling AVCC and DVCC with separate 0.1 µF ceramics eliminates digital-noise coupling into the conversion result. Power-down between conversions reduces idle current to under 1 mA, critical for isolated loop-powered modules where total quiescent budget is below 5 mA.
Empfohlen
Weigh-Scale and Load-Cell Front-End
The MAX1165AEUI+ delivers 16-bit resolution with 100 dB SINAD, which translates to a noise floor below 100 µV at the ±10 V input range — sufficient for a weigh-scale resolving 0.01% of full scale when paired with a bridge-excitation regulator and instrumentation amp. Its true-differential input rejects ground-loop noise from the load cell, and the internal 4.096 V reference stabilizes the ADC LSB weight across the industrial temperature range. Using the MAX1165AEUI+ over a discrete integrating ADC eliminates 50/60 Hz notch-filter design effort because the SAR samples at 165 ksps and outputs a 16-bit code in a single conversion.
Empfohlen
Multi-Channel Data Acquisition Card
Multi-channel DAQ cards for vibration monitoring and factory automation benefit from the MAX1165AEUI+'s parallel 16-bit output bus, which connects directly to an FPGA or DSP without serial glue logic. The 165 ksps throughput per channel, when time-multiplexed through an external analog mux, supports aggregate sample rates above 1 Msps across 8 channels. The internal reference and on-chip T/H eliminate external components, shrinking the BOM. The MAX1165AEUI+ proves especially useful in PC-based DAQ cards where the parallel bus maps directly into the FIFO memory with minimum latency.
Empfohlen
Portable Battery-Powered Data Logger
In battery-powered data loggers — handheld vibration, soil-moisture, or field-service instruments — the MAX1165AEUI+ draws under 1 mA in power-down between conversions, supporting months of standby on a single AA cell pair when sampling once per second. The 2.7 V to 5.25 V digital supply range aligns directly with lithium or alkaline packs, eliminating a boost converter. The 100 dB SINAD preserves measurement integrity in noisy field environments, and the 28-TSSOP footprint fits inside handheld enclosures with 4-layer routing.
Empfohlen
Medical Patient Monitoring Equipment
Patient monitors for ECG, SpO2, and respiration use the MAX1165AEUI+ for 16-bit acquisition of multiple vital-sign channels at latencies below 6 µs per conversion, well below the 50 ms latency budget for alarm triggering. The ±10 V common-mode tolerance accommodates the high electrode offset voltages seen across defibrillation events when paired with a front-end instrumentation amp. The MAX1165AEUI+ runs from a single 5 V analog rail and meets the noise requirements of IEC 60601-1-2 for medical electrical equipment (consult system integrator for full qualification).
Empfohlen
Motor Control Current Sensing
Three-phase motor controllers and servo drives use the MAX1165AEUI+ to sample phase currents via shunt resistors at 165 ksps, supporting 30 kHz PWM with 5+ samples per PWM period. The ±10 V input range matches typical ±5 V shunt-amplifier outputs, and the 16-bit resolution enables torque-ripple control loops requiring better than 0.05% current accuracy. The parallel interface permits direct FPGA sampling at deterministic 6 µs intervals — far better than sigma-delta latency — supporting field-oriented control (FOC) without prediction. The MAX1165AEUI+ thus bridges analog current sensing and digital motor control elegantly.
Empfohlen
Zusammenfassung der empfohlenen Produkte
Technische Referenzdaten für MAX1165AEUI+ – Vergleich, Designhinweise und Compliance-Informationen.
Auswahlhilfe
Vergleich mit Alternativen
| Parameter | Dieses Produkt | MAX1165ACUI+ | MAX1165BEUI+ | MAX1166AEUI+ | MAX1156AEUP+T |
|---|---|---|---|---|---|
| Package | TSSOP-28 | TSSOP-28 (same) | TSSOP-28 (same) | TSSOP-28 (same) | TSSOP-28 (same) |
| Brand | Maxim Integrated | Maxim Integrated | Maxim Integrated | Maxim Integrated | Maxim Integrated |
| Resolution | 16 bit | 16 bit | 16 bit | 16 bit | 12 bit |
| Throughput | 165 ksps | 165 ksps | Lower speed grade | 165 ksps | 125 ksps |
| Input Range | ±10 V differential | ±10 V differential | ±10 V differential | 0 to +10 V single-ended | ±10 V differential |
| Temperature Grade | Industrial -40 to +85 °C | Commercial 0 to +70 °C | Industrial | Industrial | Industrial |
| RoHS / Lead-Free | Yes (+ suffix) | Yes (+ suffix) | Yes (+ suffix) | Yes (+ suffix) | Yes (T suffix) |
Wichtigste Unterscheidungsmerkmale
- Industrial temperature grade in same package as commercial variant (vs. MAX1165ACUI+)
- Wide ±10 V true-differential input eliminates external signal conditioning (vs. MAX1166AEUI+)
- Higher bit depth at same pin footprint (vs. MAX1156AEUP+T)
Designhinweise
The MAX1165AEUI+ requires separate analog and digital supplies, AVCC (4.75 V to 5.25 V) and DVCC (2.7 V to 5.25 V). Place 0.1 µF ceramic decoupling capacitors as close as possible to each supply pin, plus a 4.7 µF ceramic or tantalum bulk capacitor on the REF pin to meet the 100 dB SINAD spec. Estimated: at 165 ksps with a 5 V AVCC, supply current peaks around 5 mA during conversion and falls to ~1 mA in power-down between samples — averaging below 2 mA with duty-cycling.
Do not omit the 4.7 µF bypass capacitor on the REF pin — without it, the internal 4.096 V reference is loaded by the charge-redistribution DAC and noise rises by 8-10 dB. Always enter power-down (logic high on CS for >3 clock cycles) between conversions if low quiescent is required, otherwise the part remains in full-power mode. Finally, route parallel data bus traces with 50 Ω controlled impedance and keep them away from the REF and AVCC traces to avoid coupling.
Use a star-ground topology with separate analog and digital ground planes joined at a single point beneath the MAX1165AEUI+ AGND pin. Keep the analog input traces (AIN+, AIN-) short, matched, and guarded with AGND on both sides to reject common-mode noise. Place the REF decoupling capacitor within 5 mm of the REF pin and use a wide, low-inductance trace for AVCC.
Estimated: at 165 ksps the parallel data bus toggles D0-D15 within a 6 µs conversion window; place 33 Ω series-termination resistors within 25 mm of the MAX1165AEUI+ outputs if the bus length exceeds 50 mm to the host MCU/FPGA. The RDY/INT pin should drive an edge-triggered interrupt — not be polled — to avoid missing conversions at full throughput rate.
Compliance-Informationen
RoHS and lead-free status indicated by '+' suffix per Maxim part-numbering convention. REACH compliant. AEC-Q100 not offered; for automotive applications consult factory. Halogen-free status not explicitly stated in provided web data.
