MAX1165AEUI+T - 16-Bit 200ksps Low-Power SAR ADC | Maxim Integrated
Teilenummer: MAX1165AEUI+T ✓ Aktiv| Menge | Stückpreis | Gesamt |
|---|---|---|
| 1 | $14.5 | $14,50 |
| 10 | $13.1 | $131,00 |
| 100 | $11.4 | $1.140,00 |
| 500 | $10.05 | $5.025,00 |
| 1.000 | $8.9 | $8.900,00 |
MAX1165AEUI+T Übersicht
A successive-approximation register (SAR) ADC is a class of Nyquist-rate converter that uses an internal binary-search algorithm to step a comparator-controlled DAC toward the analog input, producing one conversion per N clock cycles for N bits of resolution. The SAR architecture combines high accuracy with deterministic latency, which makes it well suited to multiplexed data-acquisition front ends, industrial process control loops, and any system that requires a stable per-sample latency without the pipeline delay of higher-speed flash or pipelined converters. The MAX1165AEUI+T belongs to the broader hierarchy of analog-to-digital converter -> data converter -> signal-chain IC -> semiconductor.
Key features include 16-bit resolution with no missing codes, ±1.0 LSB INL and ±1.0 LSB DNL (max), a 100 kHz sinad of 86 dB, an internal +4.096V reference, and automatic power-down that reduces supply current to under 10 µA between conversions at reduced throughput. The parallel interface provides 8-/16-bit bus-compatible read cycles, simplifying connection to standard microcontrollers, FPGAs, and DSPs without a serial-port block. The internal reference and compact 28-pin TSSOP footprint reduce external BOM count and PCB area versus discrete ADC designs.
Typical applications include data-acquisition systems, pen-digitizers and touch-screen controllers, battery-powered portable instruments, industrial process control, and digital signal processing front ends where deterministic latency, 16-bit resolution, and low power dissipation are required. Designers should connect AGND and DGND at a single low-impedance point, bypass AVDD and DVDD with 0.1 µF and 10 µF capacitors placed close to the pins, and respect the reference-bypass capacitor placement to achieve the datasheet-noise performance.
Drop-in-Alternativen für MAX1165AEUI+T – gleiches Gehäuse, Pin-kompatibel. Bauteile mit anderem Gehäuse, die eine PCB-Überarbeitung erfordern, sind ausgeschlossen.
Varianten dieser Serie
Modelle derselben Serie, die drop-in-kompatibel sind mit MAX1165AEUI+T (gleiche Bauform und Footprint) – abweichend in Package, Operating Temperature, Input Type, Sampling Rate, Resolution.
Schnellvergleichstool – Wählen Sie Alternativbauteile für den Direktvergleich:
MAX1166AEUI+T
✅ Drop-In📋 Referenzalternative (nicht im Katalog)
MAX1165ACUI+
✅ Drop-In✓ Auf Lager
$6.1 / Stück
Datenblatt ansehen →MAX1156AEUP+T
✅ Drop-In✓ Auf Lager
$7.8 / Stück
Datenblatt ansehen →MAX1147BEUP+T
✅ Drop-In✓ Auf Lager
$8.7 / Stück
Datenblatt ansehen →MAX1067BCEE
✅ Drop-In✓ Auf Lager
$9.4 / Stück
Datenblatt ansehen →ADS8320-HT
✅ Drop-In✓ Auf Lager
Preis auf Anfrage
Datenblatt ansehen →MAX1165AEUI+T Grenzwerte & elektrische Eigenschaften
| Auflösung | 16 bit |
| Architecture | Successive Approximation (SAR) |
| Abtastrate | 200 ksps |
| Number of Channels | 1 |
| Input Type | True-Differential (MAX1165) |
| Eingangsspannungsbereich | 0 to +10 V (MAX1165); 0 to +5 V (MAX1166) |
| Analog Supply Voltage | +5 V |
| Digital Supply Voltage | +3 V to +5 V |
| INL (max) | ±1.0 LSB |
| DNL (max) | ±1.0 LSB |
| SINAD | 86 dB at 100 kHz input |
| Reference Type | Internal 4.096 V |
| Schnittstelle | Parallel (16-bit/8-bit bus) |
| Gehäuse | 28-pin TSSOP (EUI) |
| Betriebstemperatur | -40 °C to +85 °C (Industrial) |
| Montageart | Surface Mount |
| RoHS-Status | Compliant |
MAX1165AEUI+T Pin-Konfiguration
| Pin 1 | AIN+ — Positive analog input |
| Pin 2 | AIN- — Negative analog input |
| Pin 3 | AGND — Analog ground |
| Pin 4 | AVDD — +5V analog supply |
| Pin 5 | REF — Internal 4.096V reference (decouple with 0.1uF) |
| Pin 6 | REFGND — Reference ground |
| Pin 7 | CS — Chip select (active low) |
| Pin 8 | RD — Read strobe (active low) |
| Pin 9 | WR — Write/convert start (active low) |
| Pin 10 | HBEN — High-byte enable for 8-bit bus mode |
| Pin 11 | CONVST — Conversion start |
| Pin 12 | EOC — End-of-conversion flag (active low) |
| Pin 13 | DGND — Digital ground |
| Pin 14 | DVDD — +3V to +5V digital supply |
| Pin 15 | D15 — Data bit 15 (MSB) |
| Pin 16 | D14 — Data bit 14 |
| Pin 17 | D13 — Data bit 13 |
| Pin 18 | D12 — Data bit 12 |
| Pin 19 | D11 — Data bit 11 |
| Pin 20 | D10 — Data bit 10 |
| Pin 21 | D9 — Data bit 9 |
| Pin 22 | D8 — Data bit 8 |
| Pin 23 | D7 — Data bit 7 |
| Pin 24 | D6 — Data bit 6 |
| Pin 25 | D5 — Data bit 5 |
| Pin 26 | D4 — Data bit 4 |
| Pin 27 | D3 — Data bit 3 |
| Pin 28 | D2 — Data bit 2 |
Typische Anwendungen
MAX1165AEUI+T ist geeignet für 6 Anwendungs: Industrial Data Acquisition Systems, Pen Digitizer and Touch-Screen Controllers, Battery-Powered Portable Instrumentation, Process Control and PLC Analog Input Modules, DSP Front End and Signal Processing, Medical and Scientific Instrumentation.
Industrial Data Acquisition Systems
The MAX1165AEUI+T fits industrial data acquisition front ends because of its 16-bit resolution, ±1.0 LSB INL/DNL, and 200 ksps throughput, which together deliver a 86 dB SINAD at the Nyquist bandwidth. The 0 to +10 V true-differential input range connects directly to 4-20 mA loop receivers with on-board sense resistors or to instrumentation amplifiers driving ±10 V signals, eliminating external level-shift circuitry. Placed between the transducer and a microcontroller, the parallel 16-bit interface supports deterministic single-cycle reads with no handshake overhead. Unlike sigma-delta ADCs, the SAR core provides deterministic per-sample latency, which simplifies event-triggered logging and synchronized multi-channel scanning in PLC and SCADA modules.
Empfohlen
Pen Digitizer and Touch-Screen Controllers
The MAX1165AEUI+T serves pen-digitizer and touch-screen controller applications where the 200 ksps sampling rate captures stylus position changes with sub-millisecond resolution, while the 16-bit conversion captures the full dynamic range of the electrode waveform. The parallel interface minimizes read latency, which is critical when the host controller must compute stylus coordinates within tight timing budgets. The automatic power-down feature reduces supply current below 10 µA between scans, which is essential in battery-powered stylus and tablet designs. Compared with integrating dual-slope ADCs, the SAR core settles much faster per conversion, enabling higher report rates for high-resolution digitizer surfaces.
Empfohlen
Battery-Powered Portable Instrumentation
The MAX1165AEUI+T's automatic power-down reduces quiescent current to under 10 µA between conversions, which is critical for battery-powered portable instruments that spend most of their duty cycle in standby. The internal +4.096 V reference eliminates the need for an external reference IC, which reduces BOM cost, quiescent current, and PCB area. The 200 ksps throughput supports rapid burst-mode sampling for transient capture, while the 16-bit resolution preserves the dynamic range needed for sensor front ends such as strain gauges, thermocouples, and load cells. Compared with continuous-conversion ADCs, the MAX1165AEUI+T's per-conversion current consumption is significantly lower in low-throughput modes, extending battery life in field-deployed instruments.
Empfohlen
Process Control and PLC Analog Input Modules
The MAX1165AEUI+T is well suited for analog input modules in PLC and process-control systems because its ±1.0 LSB INL and ±10 V input range map directly onto industrial transducer signals without external signal conditioning. The parallel interface allows a backplane FPGA or ASIC to multiplex multiple MAX1165AEUI+T channels and present a unified data bus to the central processor, simplifying channel-count scaling. The 86 dB SINAD at 100 kHz input frequency preserves signal fidelity for vibration, acoustic, and flow-rate measurements in industrial environments. The 28-pin TSSOP package enables high channel density on standard 4-layer PLC backplanes.
Empfohlen
DSP Front End and Signal Processing
The MAX1165AEUI+T's deterministic per-sample latency and parallel 16-bit interface make it a clean front end for digital signal processors and FPGAs implementing FFTs, filters, and control loops. The 200 ksps throughput supports audio-bandwidth signal acquisition up to 100 kHz, while the 86 dB SINAD provides more than 14 effective bits of dynamic range for spectral analysis. The internal reference and on-chip clock reduce the external component count, simplifying PCB layout for high-density DSP daughter cards. The SAR core's no-pipeline-delay property makes the MAX1165AEUI+T preferable to pipelined ADCs in real-time control and adaptive filtering applications.
Empfohlen
Medical and Scientific Instrumentation
The MAX1165AEUI+T's 16-bit no-missing-codes performance and ±1.0 LSB INL/DNL are sufficient for medical and scientific instruments such as blood analyzers, patient monitors, and bench-top chromatography data systems where low-level analog signals must be digitized with high DC accuracy. The internal reference's low drift and the 0-10 V input range support direct connection to amplified bioelectric and electrochemical sensors. The automatic power-down aids battery-powered ambulatory devices, while the parallel bus allows direct interfacing to FPGA-based signal processors. The industrial -40 °C to +85 °C temperature range suits laboratory and field-deployed clinical equipment.
Empfohlen
Zusammenfassung der empfohlenen Produkte
Technische Referenzdaten für MAX1165AEUI+T – Vergleich, Designhinweise und Compliance-Informationen.
Auswahlhilfe
Vergleich mit Alternativen
| Parameter | Dieses Produkt | MAX1166AEUI+T | MAX1165ACUI+ | MAX1156AEUP+T | MAX1147BEUP+T | ADS8320 |
|---|---|---|---|---|---|---|
| Package | TSSOP-28 | TSSOP-28 (same) | TSSOP-28 (same) | TSSOP-28 (same) | TSSOP-28 (same) | TSSOP-28 (same) |
| Brand | Maxim Integrated | Maxim Integrated (same) | Maxim Integrated (same) | Maxim Integrated (same) | Maxim Integrated (same) | Texas Instruments (cross-brand) |
| Resolution | 16 bit | 16 bit | 16 bit | 12 bit | 12 bit | 16 bit |
| Sampling Rate | 200 ksps | 200 ksps | 200 ksps | 200 ksps | 200 ksps | 100 ksps |
| Input Voltage Range | 0 to +10 V | 0 to +5 V | 0 to +10 V | 0 to +10 V | 0 to +10 V | 0 to +5 V |
| Interface | Parallel | Parallel | Parallel | Parallel | Serial | Serial (SPI) |
| INL (max) | ±1.0 LSB | ±1.0 LSB | ±1.0 LSB | ±1.0 LSB | ±1.0 LSB | ±2.0 LSB |
| Reference Type | Internal 4.096V | Internal 4.096V | Internal 4.096V | Internal 4.096V | Internal 4.096V | External |
| Operating Temperature | -40C to +85C | -40C to +85C | 0C to +70C | -40C to +85C | -40C to +85C | -40C to +85C |
Wichtigste Unterscheidungsmerkmale
- True 0-10V input range at 16-bit resolution (vs. MAX1166AEUI+T)
- Industrial -40C to +85C temperature grade (vs. MAX1165ACUI+)
- 200 ksps throughput at full 16-bit resolution (vs. ADS8320)
Designhinweise
Use a single +5V analog supply on AVDD and a separate +3V-to-+5V digital supply on DVDD. Decouple AVDD and DVDD each with a 0.1uF ceramic capacitor placed within 2mm of the respective supply pin, in parallel with a 10uF tantalum or ceramic bulk capacitor. Tie AGND and DGND together at a single low-impedance star point near the ADC. The internal 4.096V reference requires a 0.1uF ceramic bypass capacitor at the REF pin; using a smaller capacitor or omitting it degrades SINAD and INL.
Route the 16 data lines (D15..D0) together as a parallel bus with matched trace lengths to within 5mm; longer traces cause setup-time skew between bits. Keep analog input traces (AIN+, AIN-) short and guarded with a ground trace on each side to reduce common-mode noise pickup. Place the reference-bypass capacitor adjacent to the REF pin with a short, low-impedance trace to REFGND. Avoid routing digital lines under the analog input region to prevent coupling of switching transients into the input path.
Do not connect AGND and DGND at multiple points; a ground loop between the analog and digital return paths degrades INL/DNL. The CS, RD, and WR pins must observe the timing relationships in the datasheet timing diagram; asserting CS and RD simultaneously but out of sequence can produce spurious EOC pulses. Maximum throughput is 200 ksps with a 5MHz conversion clock; lower clock frequencies extend the acquisition time. Driving the inputs beyond ±15V can damage the analog input ESD clamps - add external clamping diodes for high-transient environments.
Compliance-Informationen
RoHS and REACH compliant per Maxim product declaration. Not AEC-Q100 qualified; not intended for automotive under-the-hood applications. Industrial -40C to +85C operating range per datasheet. Halogen-free status not explicitly stated in retrieved data.
