PN5120A0ET-C2J - 13.56MHz NFC Frontend, TFBGA-64 | NXP
Teilenummer: PN5120A0ET-C2J ✓ Aktiv| Menge | Stückpreis | Gesamt |
|---|---|---|
| 1 | $6.4 | $6,40 |
| 10 | $5.85 | $58,50 |
| 100 | $5.32 | $532,00 |
| 500 | $4.78 | $2.390,00 |
| 1.000 | $4.25 | $4.250,00 |
PN5120A0ET-C2J Übersicht
A Near Field Communication (NFC) frontend IC is a mixed-signal transceiver that handles modulation, demodulation, framing, anti-collision, and cryptographic acceleration for short-range (up to 10 cm) inductive-coupling wireless links at 13.56 MHz. NFC frontends sit beneath the application MCU in the wireless connectivity stack: antenna -> matching network -> frontend IC -> host MCU -> application software. They enable payments, access control, transit ticketing, and device pairing without the RF design burden of a discrete reader.
Key features of the PN5120A0ET/C2J include support for FeliCa, ISO 14443 A/B, ISO 15693, and MIFARE Classic / Ultralight / DESFire transponder families, integrated RF output stage capable of driving an externally tuned antenna loop, and a flexible host interface (SPI up to 10 Mbit/s, I2C up to 400 kbit/s, UART) with selectable IRQ signaling. An on-chip FIFO buffer of 64 bytes eases host timing, while low-power card-detection modes reduce standby consumption for battery-powered terminals.
Internally, the PN5120 uses a direct-modulation transmitter architecture with deep FIFO buffering, an adaptive receiver with automatic gain control for ISO 14443 / 15693 frames, and dedicated crypto coprocessors for MIFARE Classic CRYPTO1 and AES handling. The mixed 5 V-tolerant output drivers allow direct antenna drive from a single 3.3 V rail, while the analog front end uses a low-noise quadrature demodulator that maintains read range across temperature.
Typical applications include contactless payment terminals, transit and e-ID readers, NFC peer-to-peer bridges between a host MCU and an Android/iOS phone, access-control readers, and industrial ISO 15693 tag readers for asset tracking. The same silicon can be reused across reader/writer and card-emulation designs by firmware reconfiguration, simplifying inventory for OEMs.
When designing with the PN5120A0ET/C2J, place the external EMC filter and matching components within a few millimeters of the package RF pins to preserve the antenna Q factor. The 64-ball TFBGA requires a 4-layer PCB with a continuous ground reference under the package; power-rail decoupling must combine 100 nF and 1 uF ceramics placed as close as possible to each AVD/DVD pin pair.
Drop-in-Alternativen für PN5120A0ET-C2J – gleiches Gehäuse, Pin-kompatibel. Bauteile mit anderem Gehäuse, die eine PCB-Überarbeitung erfordern, sind ausgeschlossen.
Schnellvergleichstool – Wählen Sie Alternativbauteile für den Direktvergleich:
PN5120A0HN1/C2J
✅ Drop-In📋 Referenzalternative (nicht im Katalog)
PN5120A0ET/C2,518
✅ Drop-In📋 Referenzalternative (nicht im Katalog)
PN5120A0ET/C2
✅ Drop-In📋 Referenzalternative (nicht im Katalog)
PN5180A0ET/C1,151
✅ Drop-In📋 Referenzalternative (nicht im Katalog)
PN5120A0ET-C2J Technische Daten
| Funktion | NFC Forum-compliant reader/writer and P2P transceiver IC |
| Operating Frequency | 13.56 MHz |
| Supported Protocols | FeliCa, ISO 14443 A/B, ISO 15693, MIFARE Classic, MIFARE Ultralight, MIFARE DESFire, NFCIP-1 (ISO 18092) |
| Versorgungsspannung | 2.5 V to 3.6 V |
| Host Interface | I2C (up to 400 kbit/s), SPI (up to 10 Mbit/s), UART |
| Gehäuse | 64-ball TFBGA |
| Package Dimensions | 5.0 mm x 5.0 mm x 1.0 mm |
| Betriebstemperatur | -30C to +85C |
| FIFO Buffer | 64 bytes |
| RF Output | Differential, external antenna tuning required |
| Modulation Schemes | ASK 100% (ISO 14443), ASK 10% / 100% configurable |
| Anti-collision | Hardware-accelerated ISO 14443 Type A/B anti-collision |
| Cryptography | MIFARE Classic CRYPTO1, hardware AES (128-bit) |
| Montageart | Surface Mount |
| RoHS-Status | Compliant |
| MSL-Level | 1 (unlimited floor life) |
PN5120A0ET-C2J 5.0 mm x 5.0 mm x 1.0 mm Pinbelegungsleitfaden
Pinbelegung für PN5120A0ET-C2J (5.0 mm x 5.0 mm x 1.0 mm-Gehäuse). Pin-Nummerierung, Funktionen und Anschlussdiagramme sind im Herstellerdatenblatt definiert. Entnehmen Sie diesem den genauen Footprint und Lötrichtlinien.
Keine detaillierten Pinbelegungsdaten verfügbar für PN5120A0ET-C2J.
Siehe die Datenblatt für die vollständige Pin-Konfiguration.
Typische Anwendungen
PN5120A0ET-C2J ist geeignet für 6 Anwendungs: Contactless Payment Terminals, Transit and e-ID Readers, Access Control Readers, NFC Peer-to-Peer Bridges, ISO 15693 Asset Tracking Readers, Medical Device Pairing and Authentication.
Contactless Payment Terminals
The PN5120A0ET/C2J is widely deployed in EMVCo-compatible contactless payment terminals because it natively supports ISO 14443 A/B at 13.56 MHz with hardware-accelerated MIFARE DESFire and CRYPTO1 authentication. Its 64-byte FIFO and 10 Mbit/s SPI host interface let the terminal MCU complete a typical EMV transaction inside the 500 ms user-experience budget. The on-chip AES accelerator speeds up contactless kernel computations, while the wide 2.5 V to 3.6 V supply range simplifies power-rail design across battery-powered POS terminals. Compared to discrete 13.56 MHz reader designs, the PN5120 integrates the modulation, demodulation, framing, and anti-collision logic so engineers can focus on application-layer payment flow instead of RF hardware.
Empfohlen
Transit and e-ID Readers
For transit gate readers and e-ID verification kiosks, the PN5120A0ET/C2J delivers FeliCa, ISO 14443, and ISO 15693 support, allowing the same hardware to read transit cards, national e-ID documents, and contactless passports. Its high receiver sensitivity extends the read range across typical reader antennas, reducing mis-read rates in busy transit gates. The hardware anti-collision engine lets multiple cards in the field be enumerated quickly, which is essential for transit flows where riders tap wallets holding several cards. NXP's NFC Reader Library reference firmware accelerates development of transit readers compliant with regional standards such as OSPT Alliance, CiPurse, and Calypso.
Empfohlen
Access Control Readers
Building access readers benefit from the PN5120A0ET/C2J's small 64-ball TFBGA package (5 mm x 5 mm) which fits into slim mullion-mount reader housings. It supports the MIFARE Classic and MIFARE DESFire credential families used by most enterprise access-control systems, while its low-power standby card-detection mode keeps idle power consumption under typical battery-reader budgets. The integrated CRYPTO1 and AES accelerators offload credential authentication from the access-controller MCU, allowing faster tap-to-unlock response times. The 2.5 V to 3.6 V supply is friendly to PoE-powered access controllers that share rails with other security peripherals.
Empfohlen
NFC Peer-to-Peer Bridges
When paired with a smartphone for NFC peer-to-peer (P2P) data exchange, the PN5120A0ET/C2J implements the NFCIP-1 (ISO 18092) initiator and target roles needed for Android Beam-style or NFC Forum SNEP exchanges. The integrated LLCP and SHDLC framing reduces firmware burden on the host MCU. Combined with its 13.56 MHz carrier, the PN5120 enables Wi-Fi handover, Bluetooth pairing, and business-card exchange applications with sub-100 ms link setup. The 10 Mbit/s SPI host interface ensures the data payload path is not bottlenecked during P2P transfers.
Empfohlen
ISO 15693 Asset Tracking Readers
For industrial asset-tracking handhelds and fixed gateways, the PN5120A0ET/C2J supports ISO 15693 with its longer read range, allowing a single reader to inventory pallets of tagged items. The hardware anti-collision engine accelerates inventory commands that scan hundreds of tags in a single RF burst. Combined with the host MCU's file system, a PN5120-based reader can store and upload inventory logs over USB or Ethernet between scan sessions. The wide 2.5 V to 3.6 V supply is tolerant of the unregulated battery rails common in handheld industrial readers.
Empfohlen
Medical Device Pairing and Authentication
Medical devices such as infusion pumps, glucose meters, and patient-worn sensors use the PN5120A0ET/C2J for tap-to-pair authentication with clinician tablets and NFC-programmable configuration cards. The integrated CRYPTO1 and AES engines provide a hardware root-of-trust for medical device firmware updates. The wide 2.5 V to 3.6 V supply range simplifies integration with battery-powered medical devices that share a single Li-ion regulator output. The compact 64-ball TFBGA package fits inside small wearable enclosures where board real estate is constrained.
Empfohlen
Zusammenfassung der empfohlenen Produkte
Technische Referenzdaten für PN5120A0ET-C2J – Vergleich, Designhinweise und Compliance-Informationen.
Auswahlhilfe
Vergleich mit Alternativen
| Parameter | Dieses Produkt | PN5120A0HN1/C2J | PN5120A0ET/C2,518 | PN5120A0ET/C2 | PN5180A0ET/C1,151 |
|---|---|---|---|---|---|
| Package | 64-TFBGA (5x5 mm) | 64-TFBGA (5x5 mm) - same | 64-TFBGA (5x5 mm) - same | 64-TFBGA (5x5 mm) - same | 64-TFBGA (5x5 mm) - same |
| Brand | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors | NXP Semiconductors |
| Operating Frequency | 13.56 MHz | 13.56 MHz | 13.56 MHz | 13.56 MHz | 13.56 MHz |
| Supply Voltage | 2.5 V to 3.6 V | 2.5 V to 3.6 V | 2.5 V to 3.6 V | 2.5 V to 3.6 V | 2.5 V to 5.5 V |
| Host Interface | I2C, SPI, UART | I2C, SPI, UART | I2C, SPI, UART | I2C, SPI, UART | SPI, I2C |
| Supported Protocols | FeliCa, ISO 14443 A/B, ISO 15693, MIFARE, NFCIP-1 | FeliCa, ISO 14443 A/B, ISO 15693, MIFARE, NFCIP-1 | FeliCa, ISO 14443 A/B, ISO 15693, MIFARE, NFCIP-1 | FeliCa, ISO 14443 A/B, ISO 15693, MIFARE, NFCIP-1 | ISO 14443 A/B, ISO 15693, FeliCa, NFCIP-1, MIFARE |
| RF Output Power | Typical 0 dBm into 50 ohm | Typical 0 dBm into 50 ohm | Typical 0 dBm into 50 ohm | Typical 0 dBm into 50 ohm | Up to +5 dBm (configurable), higher output power |
| Cryptography | CRYPTO1, hardware AES (128-bit) | CRYPTO1, hardware AES (128-bit) | CRYPTO1, hardware AES (128-bit) | CRYPTO1, hardware AES (128-bit) | CRYPTO1, hardware AES (128-bit), plus TRNG |
| Pin-to-Pin Compatible | Reference part | Yes - same 64-TFBGA ball map | Yes - same silicon and ball map | Yes - same silicon and ball map | Yes - same 64-TFBGA ball map, different command set |
Wichtigste Unterscheidungsmerkmale
- Established and widely supported legacy NFC frontend (vs. PN5180A0ET/C1,151)
- Industry-standard NFC Forum compliance baseline (vs. ST25R3916-B (STMicroelectronics))
- Triple-mode host interface in a single SKU (vs. PN5180A0ET/C1,151 (SPI+I2C only))
Designhinweise
Place the EMC filter (typically a 100 ohm ferrite + 100 pF + 68 pF pi-network) and antenna-matching components within 3-5 mm of the package RF pins to preserve antenna Q. Route the differential RF traces as a 50 ohm differential pair with continuous ground reference on the layer directly below, and avoid routing any digital signals under the antenna loop. The exposed pad of the TFBGA should be soldered to a ground copper pour stitched with multiple thermal vias to reduce ground impedance and improve RF return paths.
Use a separate LDO or ferrite bead to isolate AVDD from DVDD, even though both rails share the same 2.5 V to 3.6 V range. Place a 1 uF X7R ceramic plus 100 nF X7R ceramic on each AVDD pin pair and on each DVDD pin pair, located as close to the package balls as the PCB design rules allow. The PN5120 draws peak current during RF field-on events, so the bulk decoupling capacitor should be at least 10 uF to prevent supply droop during ISO 14443 anti-collision bursts.
For SPI host connections, keep clock rise/fall times under 5 ns and ensure the SPI bus does not exceed 10 Mbit/s in single-bit mode. Route SPI traces over a continuous ground reference and add 33 ohm series damping resistors if the bus length exceeds 50 mm. The IRQ output is an open-drain signal; provide an external 10 kohm pull-up to the host supply rail and route the IRQ trace away from RF traces to avoid coupling noise into the receiver.
Do not operate the PN5120 without the external EMC filter and matching network - the receiver is sensitive to conducted noise and will show reduced read range if the filter is omitted. The IFSel pins that select host interface mode must be tied to logic levels before power-up; floating IFSel pins cause boot failures. The TX1/TX2 pins require DC blocking capacitors (typically 1 nF) - omitting these blocks RF output entirely. Finally, respect the maximum input voltage of 3.6 V; the host interface pins are NOT 5 V tolerant and must be level-shifted if used with a 5 V MCU.
Compliance-Informationen
RoHS and REACH compliant per NXP product page; lead-free reflow profile per JEDEC J-STD-020. Not AEC-Q100 qualified - this is a commercial-grade NFC frontend for non-automotive applications.
