PSD853F2-90J - 1Mbit Flash ISP PSD, 5V, 90ns, 52-PLCC | STMicroelectronics
Teilenummer: PSD853F2-90J ✗ Abgekündigt| Menge | Stückpreis | Gesamt |
|---|---|---|
| 1 | $18.5 | $18,50 |
| 10 | $16.2 | $162,00 |
| 100 | $13.85 | $1.385,00 |
| 500 | $11.4 | $5.700,00 |
| 1.000 | $9.95 | $9.950,00 |
PSD853F2-90J Übersicht
A Programmable System Device (PSD) belongs to the broader category of memory-plus-logic ICs and sits hierarchically between discrete flash memory and a microcontroller in embedded designs. By consolidating non-volatile storage, volatile memory, and configurable I/O/PLD logic into one package, PSD devices remove the need for external memory chips, latches, and glue logic that historically accompanied 8-bit MCU designs. The PSD853F2 family specifically targets cost-sensitive 8051, 68HC11, and other 8-bit MCU platforms that require field-upgradeable firmware storage without sacrificing board space.
Key features of the PSD853F2-90J include its dual-bank flash architecture supporting simultaneous read-while-write operation, an integrated PLD with macro cells for address decoding and chip-select logic, 27 programmable I/O pins, JTAG/ISP programming interfaces, and a 90 ns access time suitable for 8-bit MCU bus speeds. The 52-pin PLCC (J-bend) package provides robust through-hole-style soldering suitable for industrial and commercial environments up to 70 degrees C operating temperature.
The internal architecture combines a flash memory controller, SRAM block, dual PLD arrays (DPLD and GPLD), and I/O ports under a unified configuration register space accessed through the MCU bus. The flash memory uses a sector-erase architecture with hardware write protection, while the PLD logic implements sum-of-products expressions evaluated on every bus cycle to generate chip selects and steering logic automatically.
Typical applications for the PSD853F2-90J include industrial control panels, point-of-sale terminals, automotive body controllers (non-safety), legacy 8051 firmware expansion modules, and consumer appliance controllers. The integrated PLD enables designers to replace 2-4 discrete logic chips with a single programmable device.
When designing, engineers should verify that the MCU bus timing meets the 90 ns access time requirement and that the JTAG/ISP programming header is accessible on the PCB for firmware updates. The PSDsoft Express configuration tool is required to define flash partitioning, PLD equations, and I/O assignments.
This page synthesizes distributor stock, parametric alternatives, and design notes that go beyond the manufacturer datasheet, including practical comparisons to similar PSD family devices and recommendations for new designs versus legacy migrations.
Drop-in-Alternativen für PSD853F2-90J – gleiches Gehäuse, Pin-kompatibel. Bauteile mit anderem Gehäuse, die eine PCB-Überarbeitung erfordern, sind ausgeschlossen.
Schnellvergleichstool – Wählen Sie Alternativbauteile für den Direktvergleich:
PSD853F2-90JI
✅ Drop-In📋 Referenzalternative (nicht im Katalog)
PSD854F2-90J
✅ Drop-In📋 Referenzalternative (nicht im Katalog)
PSD834F2-90J
✅ Drop-In📋 Referenzalternative (nicht im Katalog)
PSD813F1-90JI
✅ Drop-In📋 Referenzalternative (nicht im Katalog)
PSD4235G2-90U
✅ Drop-In📋 Referenzalternative (nicht im Katalog)
PSD853F2-90J Grenzwerte & elektrische Eigenschaften
| Product Type | Programmable System Device (PSD) with Flash Memory |
| Speichertyp | Flash (Primary + Secondary) + SRAM |
| Primary Flash Size | 1 Mbit (8 uniform sectors) |
| Secondary Flash Size | 256 Kbit (4 uniform sectors) |
| Access Time | 90 ns |
| Versorgungsspannung | 4.5 V to 5.5 V |
| Programmable I/O Pins | 27 |
| Integrated PLD | Yes (DPLD + GPLD) |
| In-System Programming | Yes (JTAG/ISP) |
| Betriebstemperatur | 0C to +70C (commercial) |
| Gehäuse | 52-PLCC (19.1 x 19.1 mm) |
| Montageart | Surface Mount (J-lead) |
| Target MCU Interface | 8-bit MCU bus (8051, 68HC11, etc.) |
| Lebenszyklusstatus | Obsolete (per distributor listings) |
PSD853F2-90J Pin-Konfiguration
| Pin 1 | VCC — +5V power supply |
| Pin 2 | PA0 — Programmable I/O Port A bit 0 |
| Pin 3 | PA1 — Programmable I/O Port A bit 1 |
| Pin 4 | PA2 — Programmable I/O Port A bit 2 |
| Pin 5 | PA3 — Programmable I/O Port A bit 3 |
| Pin 6 | PA4 — Programmable I/O Port A bit 4 |
| Pin 7 | PA5 — Programmable I/O Port A bit 5 |
| Pin 8 | PA6 — Programmable I/O Port A bit 6 |
| Pin 9 | PA7 — Programmable I/O Port A bit 7 |
| Pin 10 | GND — Ground |
| Pin 11 | PB0 — Programmable I/O Port B bit 0 |
| Pin 12 | PB1 — Programmable I/O Port B bit 1 |
| Pin 13 | PB2 — Programmable I/O Port B bit 2 |
| Pin 14 | PB3 — Programmable I/O Port B bit 3 |
| Pin 15 | PC0 — Programmable I/O Port C bit 0 |
| Pin 16 | PC1 — Programmable I/O Port C bit 1 |
| Pin 17 | PC2 — Programmable I/O Port C bit 2 |
| Pin 18 | PC3 — Programmable I/O Port C bit 3 |
| Pin 19 | PC4 — Programmable I/O Port C bit 4 |
| Pin 20 | PC5 — Programmable I/O Port C bit 5 |
| Pin 21 | PC6 — Programmable I/O Port C bit 6 |
| Pin 22 | PC7 — Programmable I/O Port C bit 7 |
| Pin 23 | PD0 — Programmable I/O Port D bit 0 |
| Pin 24 | PD1 — Programmable I/O Port D bit 1 |
| Pin 25 | A0 — Address bus bit 0 |
| Pin 26 | A1 — Address bus bit 1 |
| Pin 27 | A2 — Address bus bit 2 |
| Pin 28 | A3 — Address bus bit 3 |
| Pin 29 | A4 — Address bus bit 4 |
| Pin 30 | A5 — Address bus bit 5 |
| Pin 31 | A6 — Address bus bit 6 |
| Pin 32 | A7 — Address bus bit 7 |
| Pin 33 | A8 — Address bus bit 8 |
| Pin 34 | A9 — Address bus bit 9 |
| Pin 35 | A10 — Address bus bit 10 |
| Pin 36 | A11 — Address bus bit 11 |
| Pin 37 | A12 — Address bus bit 12 |
| Pin 38 | A13 — Address bus bit 13 |
| Pin 39 | A14 — Address bus bit 14 |
| Pin 40 | A15 — Address bus bit 15 |
| Pin 41 | DQ0 — Data bus bit 0 |
| Pin 42 | DQ1 — Data bus bit 1 |
| Pin 43 | DQ2 — Data bus bit 2 |
| Pin 44 | DQ3 — Data bus bit 3 |
| Pin 45 | DQ4 — Data bus bit 4 |
| Pin 46 | DQ5 — Data bus bit 5 |
| Pin 47 | DQ6 — Data bus bit 6 |
| Pin 48 | DQ7 — Data bus bit 7 |
| Pin 49 | PSEN — Program Store Enable (active low) |
| Pin 50 | RD — Read strobe (active low) |
| Pin 51 | WR — Write strobe (active low) |
| Pin 52 | RESET — Device reset (active low) |
Typische Anwendungen
PSD853F2-90J ist geeignet für 6 Anwendungs: Industrial Control Panels with 8-bit MCU, Point-of-Sale (POS) Terminal Firmware Storage, Consumer Appliance Controllers, Automotive Body Control Modules (Non-Safety), Legacy 8051 Firmware Expansion Modules, Security and Access Control Panels.
Industrial Control Panels with 8-bit MCU
The PSD853F2-90J integrates 1 Mbit flash, SRAM, and programmable logic into one chip, making it ideal for industrial control panels built around 8051 or 68HC11 microcontrollers. The dual-bank flash architecture supports field firmware updates via JTAG/ISP without removing the controller from the panel, while the integrated PLD generates chip-select logic for external peripherals, eliminating 2-3 discrete logic ICs. The 90 ns access time matches standard 8-bit MCU bus speeds, allowing zero-wait-state code execution in panels with up to 256 KB firmware.
Empfohlen
Point-of-Sale (POS) Terminal Firmware Storage
POS terminals need reliable field-upgradable firmware storage with integrated I/O for keypads, displays, and card readers. The PSD853F2-90J provides 1 Mbit of primary flash for application code, 256 Kbit of secondary flash for bootloader or transaction logs, and 27 programmable I/O pins that map directly to keypad matrix, LCD interface, and serial peripherals. The 52-PLCC package supports socketed deployment for serviceability, and the JTAG ISP interface enables in-the-field firmware updates without removing the terminal from service.
Empfohlen
Consumer Appliance Controllers
Home appliances such as washing machines, dishwashers, and HVAC thermostats benefit from the PSD853F2-90J's integration of flash, RAM, and logic in a single PLCC package. The commercial temperature grade (0C to +70C) suits indoor appliance environments, and the 90 ns access time keeps total BOM cost low by eliminating external memory chips. The integrated PLD handles washing-cycle timing logic and relay sequencing through the 27 programmable I/O pins, replacing discrete 74HC-series logic.
Empfohlen
Automotive Body Control Modules (Non-Safety)
Legacy automotive body controllers for door locks, window lifts, and lighting use 8-bit MCUs with PSD expansion. The PSD853F2-90J provides firmware storage and I/O expansion for these modules, though designers should select the PSD853F2-90JI variant for under-hood environments. The integrated PLD implements LIN bus steering logic and PWM generation for motor control, replacing multiple external components. The 52-PLCC package with industrial temperature grade supports automotive operating conditions when the -90JI suffix is specified.
Empfohlen
Legacy 8051 Firmware Expansion Modules
The PSD853F2-90J was originally designed to extend the limited program memory of 8051-family microcontrollers such as the NXP P87C591VFA. In legacy firmware expansion modules, the PSD acts as bank-switched external code memory with the integrated PLD generating the upper address lines for bank selection. The 1 Mbit primary flash holds up to 128 KB of application code accessible via standard MOVC instructions, and the 256 Kbit secondary flash stores bootloader or version history for field updates.
Empfohlen
Security and Access Control Panels
Security alarm panels and access control systems use 8-bit MCUs paired with PSD devices for firmware storage and multi-zone I/O handling. The PSD853F2-90J provides 27 programmable I/O pins to interface with door sensors, keypads, sirens, and communication modules, while the 1 Mbit flash stores zone configuration and event logs. The dual-bank flash enables secure firmware updates where the secondary bank holds the new image while the primary continues to run, then a watchdog-triggered swap activates the new code on next reset.
Empfohlen
Zusammenfassung der empfohlenen Produkte
Technische Referenzdaten für PSD853F2-90J – Vergleich, Designhinweise und Compliance-Informationen.
Auswahlhilfe
Vergleich mit Alternativen
| Parameter | Dieses Produkt | PSD853F2-90JI | PSD854F2-90J | PSD834F2-90J | PSD813F1-90JI | PSD4235G2-90U |
|---|---|---|---|---|---|---|
| Package | 52-PLCC | 52-PLCC (same) | 52-PLCC (same) | 52-PLCC (same) | 52-PLCC (same) | 52-PLCC (same) |
| Brand | STMicroelectronics | STMicroelectronics | STMicroelectronics | STMicroelectronics | STMicroelectronics | STMicroelectronics |
| Primary Flash Size | 1 Mbit | 1 Mbit (same) | 2 Mbit (+100%) | 1 Mbit (same) | 1 Mbit (same) | 4 Mbit (+300%) |
| Secondary Flash Size | 256 Kbit | 256 Kbit (same) | 256 Kbit (same) | 256 Kbit (same) | 256 Kbit (same) | 256 Kbit (same) |
| Access Time | 90 ns | 90 ns (same) | 90 ns (same) | 90 ns (same) | 90 ns (same) | 90 ns (same) |
| Operating Temperature | 0C to +70C (commercial) | -40C to +85C (industrial) | 0C to +70C (commercial) | 0C to +70C (commercial) | -40C to +85C (industrial) | -40C to +85C (industrial) |
| Programmable I/O Pins | 27 | 27 (same) | 27 (same) | 27 (same) | 27 (same) | 27 (same) |
| Integrated PLD | Yes (DPLD + GPLD) | Yes (same) | Yes (same) | Yes (same) | Yes (same) | Yes (enhanced) |
| In-System Programming | JTAG/ISP | JTAG/ISP (same) | JTAG/ISP (same) | JTAG/ISP (same) | JTAG/ISP (same) | JTAG/ISP (same) |
| Supply Voltage | 4.5V to 5.5V | 4.5V to 5.5V (same) | 4.5V to 5.5V (same) | 4.5V to 5.5V (same) | 4.5V to 5.5V (same) | 3.0V to 3.6V or 4.5V to 5.5V |
Wichtigste Unterscheidungsmerkmale
- Same-package density upgrade path (vs. PSD854F2-90J)
- Dual-bank flash architecture (vs. Discrete flash + SRAM + 74HC logic)
- Integrated PLD vs external glue logic (vs. Discrete 74HC138/74HC139 chip-select decoders)
Designhinweise
The 52-PLCC package requires a PLCC socket (e.g., 3M Textool or AMP Incert) for socketed prototyping and field service. When soldering directly to the PCB, use a J-lead footprint with pad pitch of 1.27 mm (50 mil) and ensure the central thermal/exposed area on the bottom of the PLCC is left unsoldered or connected to a small thermal pad to prevent mechanical stress. Decoupling: place one 100 nF ceramic capacitor directly between VCC (pin 1) and GND (pin 10) within 5 mm of the package, plus a 10 uF tantalum bulk capacitor on the same supply rail.
Do not confuse the PSD853F2-90J (commercial 0C to +70C) with the PSD853F2-90JI (industrial -40C to +85C) when ordering for automotive or outdoor applications. The PSD853F2-90J is obsolete and not recommended for new designs; for new projects use the PSD4235G2-90U family (4 Mbit flash) or migrate to STM32 microcontrollers with integrated flash and configurable peripherals. When using the integrated PLD, ensure the PSDsoft Express-generated JEDEC file is loaded before programming the flash, otherwise the chip selects will not match the firmware memory map.
Address and data bus traces (A0-A15, DQ0-DQ7) must be kept short and matched in length to within 10 mm to meet the 90 ns access time requirement. According to the ST datasheet timing section, tAA (address-to-output valid) is 90 ns maximum, so any added bus capacitance from long traces will push access time beyond specification at 8-bit MCU clock rates above 11 MHz. Place the PSD853F2-90J within 50 mm of the host MCU and use a ground plane on the layer directly beneath the bus traces.
The PSD853F2-90J operates from a single 4.5V to 5.5V supply; an LDO regulator such as the NCP177AMX330TCG (3.3V) is NOT suitable and a 5V regulator must be used. According to the ST datasheet, VCC must be decoupled at the package pin with a 100 nF ceramic plus 10 uF tantalum bulk. During flash programming, peak current can reach 50 mA per bank, so the 5V regulator must supply at least 200 mA peak if both banks are programmed simultaneously.
Compliance-Informationen
Compliance information for PSD853F2-90J is not explicitly stated in the verified distributor listings. STMicroelectronics legacy PSD family parts were generally RoHS compliant for commercial temperature grades produced after 2005, but this should be verified against the specific lot date code before use in RoHS-restricted applications. AEC-Q100 qualification is not applicable to this commercial-grade PSD.
