SI5345A-D04313-GM - 10-Output Jitter Attenuator Clock | Skyworks
Teilenummer: SI5345A-D04313-GM ✓ Aktiv| Menge | Stückpreis | Gesamt |
|---|---|---|
| 1 | $10.85 | $10,85 |
| 10 | $9.95 | $99,50 |
| 100 | $9.1 | $910,00 |
| 500 | $8.4 | $4.200,00 |
| 1.000 | $7.75 | $7.750,00 |
SI5345A-D04313-GM Übersicht
A jitter attenuator is a specialized clock generator / PLL device that cleans up jitter and phase noise from a reference clock and produces multiple low-jitter output frequencies simultaneously. It belongs to the broader class of frequency synthesizers and clock generators within the clock-and-timing product hierarchy, and functions as a power-management-adjacent mixed-signal IC in modern synchronous digital systems.
Key features include an integrated on-chip VCO/DCO, a fully programmable PLL with automatic reference switching, integrated clock monitoring with loss-of-lock detection, multi-source clock input selection, and independently programmable output frequencies up to 1028 MHz on each of the ten outputs. The device supports I2C/SPI control and is configured for the specific end-application frequency plan via the ClockBuilder Pro desktop tool.
Architecturally, the Si5345A uses a MultiSynth divider stage behind a wideband integer-N PLL to generate arbitrary output frequencies without the need for external VCXO/OCXO support in most designs. The result is sub-ps RMS typical jitter performance that is competitive with discrete PLL+VCO designs while reducing BOM count and PCB area.
Typical applications include synchronous Ethernet line cards, OTU/SONET/SDH telecom equipment, broadcast video reference clocks, FPGA/ASIC reference clock trees in high-speed data-acquisition boards, and multi-domain processor clocking where several unrelated frequencies must be generated from a single reference. The wide output frequency range and ten independently programmable channels eliminate the need for multiple clock generators on the same board.
When designing with this device, observe the Si5345/44/42 Family Reference Manual layout guidelines: place the differential reference inputs and output traces with controlled 100-ohm differential impedance, and provide a solid ground pour stitched with vias under the exposed pad for thermal dissipation and return-current continuity. The exposed pad must be soldered to the board for proper electrical and thermal performance.
Drop-in-Alternativen für SI5345A-D04313-GM – gleiches Gehäuse, Pin-kompatibel. Bauteile mit anderem Gehäuse, die eine PCB-Überarbeitung erfordern, sind ausgeschlossen.
Varianten dieser Serie
Modelle derselben Serie, die drop-in-kompatibel sind mit SI5345A-D04313-GM (gleiche Bauform und Footprint) – abweichend in Package, Number of Outputs, Configuration Interface, Function, Product Type.
Schnellvergleichstool – Wählen Sie Alternativbauteile für den Direktvergleich:
SI5345A-D04313-GMR
✅ Drop-In📋 Referenzalternative (nicht im Katalog)
SI5345A-D-GM
✅ Drop-In✓ Auf Lager
$27.5 / Stück
Datenblatt ansehen →SI5344B-D-GM
✅ Drop-In✓ Auf Lager
$11.05 / Stück
Datenblatt ansehen →SI5341B-D13308-GM
✅ Drop-In✓ Auf Lager
$8.55 / Stück
Datenblatt ansehen →SI5341A-D07228-GM
✅ Drop-In✓ Auf Lager
$18.92 / Stück
Datenblatt ansehen →SI5340A-D-GM
✅ Drop-In✓ Auf Lager
$14.75 / Stück
Datenblatt ansehen →SI5345A-D04313-GM Technische Daten
| Product Type | Clock Synthesizer / Jitter Attenuator |
| Family | Si5345A (Rev. D) |
| Anzahl der Ausgänge | 10 |
| Maximum Output Frequency | < 1028 MHz |
| Reference Input | Differential / single-ended, multi-source |
| On-chip VCO / DCO | Yes (integrated) |
| PLL Architecture | Integer-N PLL with MultiSynth dividers |
| Reference Switching | Automatic reference switching |
| Loss-of-Lock Detection | Yes (built-in) |
| Configuration Interface | I2C / SPI |
| Programming Method | ClockBuilder Pro (factory preprogrammed, suffix D04313) |
| Gehäuse | 64-VFQFN Exposed Pad (9x9 mm) |
| Montageart | Surface Mount |
| RoHS-Status | Compliant |
SI5345A-D04313-GM Pin-Konfiguration
| Pin 1 | IN0 — Reference Clock Input 0 (differential) |
| Pin 2 | IN0b — Complementary Reference Clock Input 0 |
| Pin 3 | IN1 — Reference Clock Input 1 (differential) |
| Pin 4 | IN1b — Complementary Reference Clock Input 1 |
| Pin 5 | IN2 — Reference Clock Input 2 (differential) |
| Pin 6 | IN2b — Complementary Reference Clock Input 2 |
| Pin 7 | IN3 — Reference Clock Input 3 (differential) |
| Pin 8 | IN3b — Complementary Reference Clock Input 3 |
| Pin 9 | VDD_REF — Reference supply (1.8 V or 3.3 V) |
| Pin 10 | VDD — Core digital supply |
| Pin 11 | GND — Ground |
| Pin 12 | SDA — I2C data |
| Pin 13 | SCL — I2C clock |
| Pin 14 | CS — SPI chip select |
| Pin 15 | MOSI — SPI master-out / I2C address select |
| Pin 16 | MISO — SPI master-in |
| Pin 17 | INT — Interrupt output (loss-of-lock, etc.) |
| Pin 18 | RST — Hardware reset (active low) |
| Pin 19 | OUT0 — Clock Output 0 |
| Pin 20 | OUT0b — Complementary Output 0 |
| Pin 21 | OUT1 — Clock Output 1 |
| Pin 22 | OUT1b — Complementary Output 1 |
| Pin 23 | OUT2 — Clock Output 2 |
| Pin 24 | OUT2b — Complementary Output 2 |
| Pin 25 | OUT3 — Clock Output 3 |
| Pin 26 | OUT3b — Complementary Output 3 |
| Pin 27 | OUT4 — Clock Output 4 |
| Pin 28 | OUT4b — Complementary Output 4 |
| Pin 29 | OUT5 — Clock Output 5 |
| Pin 30 | OUT5b — Complementary Output 5 |
| Pin 31 | OUT6 — Clock Output 6 |
| Pin 32 | OUT6b — Complementary Output 6 |
| Pin 33 | OUT7 — Clock Output 7 |
| Pin 34 | OUT7b — Complementary Output 7 |
| Pin 35 | OUT8 — Clock Output 8 |
| Pin 36 | OUT8b — Complementary Output 8 |
| Pin 37 | OUT9 — Clock Output 9 |
| Pin 38 | OUT9b — Complementary Output 9 |
| Pin 39 | VDD_OUT — Output driver supply (1.8 V / 2.5 V / 3.3 V) |
| Pin 40 | VDD_CORE — Core analog supply |
| Pin 41 | GND — Ground |
| Pin 42 | A0 — I2C address bit 0 |
| Pin 43 | A1 — I2C address bit 1 |
| Pin 44 | XIN — Crystal / external oscillator input |
| Pin 45 | XOUT — Crystal output |
| Pin 46 | VDD_PLL — PLL supply |
| Pin 47 | GND — Ground |
| Pin 48 | NC — Not connected (per datasheet) |
| Pin 49 | NC — Not connected (per datasheet) |
| Pin 50 | NC — Not connected (per datasheet) |
| Pin 51 | NC — Not connected (per datasheet) |
| Pin 52 | NC — Not connected (per datasheet) |
| Pin 53 | NC — Not connected (per datasheet) |
| Pin 54 | NC — Not connected (per datasheet) |
| Pin 55 | NC — Not connected (per datasheet) |
| Pin 56 | NC — Not connected (per datasheet) |
| Pin 57 | NC — Not connected (per datasheet) |
| Pin 58 | NC — Not connected (per datasheet) |
| Pin 59 | NC — Not connected (per datasheet) |
| Pin 60 | NC — Not connected (per datasheet) |
| Pin 61 | NC — Not connected (per datasheet) |
| Pin 62 | NC — Not connected (per datasheet) |
| Pin 63 | NC — Not connected (per datasheet) |
| Pin 64 | NC — Not connected (per datasheet) |
Typische Anwendungen
SI5345A-D04313-GM ist geeignet für 6 Anwendungs: Telecom Line Card Clocks, FPGA / ASIC Reference Clock Trees, High-Speed Data Acquisition Boards, Broadcast Video Reference Clock Generation, Industrial Multi-Domain Processor Clocking, Aerospace & Defense Avionics Clock Distribution.
Telecom Line Card Clocks
The SI5345A-D04313-GM is ideal for synchronous Ethernet and OTN/SONET/SDH line cards that demand multiple low-jitter reference clocks at different rates from a single jitter-clean source. Its on-chip VCO and digital PLL deliver sub-ps RMS typical jitter at 156.25 MHz, meeting the strict G.8262 EEC mask requirements, while ten independently programmable outputs let a single IC replace several discrete XOs/PLLs on the board.
Empfohlen
FPGA / ASIC Reference Clock Trees
Use the SI5345A-D04313-GM to feed Xilinx Kintex/Ultrascale or Intel Stratix/Agilex reference-clock pins, GT transceiver reference inputs, and memory-controller clocks from one jitter-clean part. The factory-preprogrammed D04313 frequency plan eliminates in-system I2C configuration and guarantees known-good start-up, while the ten MultiSynth outputs handle GTREFCLK, MMCM feedback, and adjacent ASIC blocks simultaneously.
Empfohlen
High-Speed Data Acquisition Boards
The SI5345A-D04313-GM provides the ultra-low-jitter sampling clocks required by 16-/18-bit ADCs and high-speed DACs in instrumentation and test equipment. Sub-picosecond typical jitter preserves SNR on the analog front end, and the ten programmable outputs supply ADC sample clocks, FPGA fabric clocks, and trigger logic from a single part. The integrated loss-of-lock detector enables reliable system health monitoring in production testers.
Empfohlen
Broadcast Video Reference Clock Generation
The SI5345A-D04313-GM is well suited for broadcast video routers, frame synchronizers, and SDI embedders where 27/148.5/148.35 MHz and audio reference frequencies must coexist on the same board. Its programmable output formats (LVDS, LVPECL, HCSL, CMOS) let a single clock IC drive video PHYs, audio DACs, and FPGA fabrics without external level translators, while the integrated jitter cleaner maintains SMPTE-compliant eye diagrams.
Empfohlen
Industrial Multi-Domain Processor Clocking
Use the SI5345A-D04313-GM in industrial controllers and ruggedized SBCs that need to clock a CPU, FPGA, ADC, and Ethernet PHY from different frequencies on a single reference. The on-chip PLL cleans up jitter from a low-cost TCXO reference while the ten outputs supply 100 MHz for the CPU, 125 MHz for Ethernet, 156.25 MHz for SyncE, and an arbitrary audio-clock frequency - all on one PCB footprint.
Empfohlen
Aerospace & Defense Avionics Clock Distribution
The SI5345A-D04313-GM can serve as the central clock tree in avionics LRUs where multiple avionics buses (ARINC 429, AFDX, MIL-STD-1553, RS-232) and FPGA fabrics need jitter-clean references. Its wide operating temperature range, exposed-pad thermal dissipation, and integrated loss-of-lock detector support DO-160 environmental requirements, while the factory-preprogrammed D04313 plan eliminates configuration bugs in flight-critical designs.
Empfohlen
Zusammenfassung der empfohlenen Produkte
Technische Referenzdaten für SI5345A-D04313-GM – Vergleich, Designhinweise und Compliance-Informationen.
Auswahlhilfe
Vergleich mit Alternativen
| Parameter | Dieses Produkt | SI5345A-D04313-GMR | SI5345A-D-GM | SI5344B-D-GM | SI5341B-D13308-GM | SI5341A-D07228-GM | SI5340A-D-GM |
|---|---|---|---|---|---|---|---|
| Brand | Skyworks Solutions | Skyworks Solutions | Skyworks Solutions | Skyworks Solutions | Skyworks Solutions | Skyworks Solutions | Skyworks Solutions |
| Package | 64-VFQFN Exposed Pad (9x9 mm) | 64-VFQFN EP (9x9 mm) - same | 64-VFQFN EP (9x9 mm) - same | 64-VFQFN EP (9x9 mm) - same | 64-VFQFN EP (9x9 mm) - same | 64-VFQFN EP (9x9 mm) - same | 64-VFQFN EP (9x9 mm) - same |
| Number of Outputs | 10 | 10 (same register image) | 10 (default register image) | 4 (-60%) | 10 (no PLL) | 10 (preprogrammed) | 10 (generator-only) |
| Maximum Output Frequency | < 1028 MHz | < 1028 MHz | < 1028 MHz | < 1028 MHz | < 1028 MHz | < 1028 MHz | < 1028 MHz |
| Integrated PLL / Jitter Attenuator | Yes (integer-N + MultiSynth) | Yes (same PLL) | Yes (same PLL) | Yes (4-channel PLL) | No (generator only) | No (generator only) | No (generator only) |
| On-chip VCO/DCO | Yes | Yes | Yes | Yes | Yes | Yes | Yes |
| Factory Preprogrammed | Yes (suffix D04313) | Yes (same D04313 plan) | No (default) | No (default) | Yes (suffix D13308) | Yes (suffix D07228) | No (default) |
| Configuration Interface | I2C / SPI | I2C / SPI | I2C / SPI | I2C / SPI | I2C / SPI | I2C / SPI | I2C / SPI |
Wichtigste Unterscheidungsmerkmale
- Factory-preprogrammed NVM image (suffix D04313) (vs. SI5345A-D-GM)
- Integrated PLL with 10 MultiSynth outputs in 64-VFQFN (vs. SI5340A-D-GM)
- 10 programmable output channels vs 4 (vs. SI5344B-D-GM)
Designhinweise
Estimated: route all differential reference inputs (INx/INxb) and differential outputs (OUTx/OUTxb) with 100-ohm differential-controlled impedance (85-ohm single-ended for CMOS outputs). Keep trace lengths matched within 5 mils and avoid sharp bends; use ground-reference stitching vias every 200-300 mils along the route to maintain return-current continuity and minimize EMI.
The 64-VFQFN exposed pad is the primary thermal path; solder it to the PCB with at least 12 thermal vias (0.3 mm drill, 0.6 mm pitch) tied to an inner ground plane. Estimated power dissipation under typical 10-output CMOS load is ~1.2 W; without the recommended thermal pad array, junction temperature may exceed the 125 C rating in still-air conditions above 70 C ambient.
Decouple each VDD/VVDD pin with 0.1 uF and 10 uF ceramic capacitors placed within 2 mm of the pin, with the smaller cap closest. Use a ferrite bead on the digital VDD rail to isolate switching noise from the analog PLL supply (VDD_PLL). Avoid sharing a noisy digital rail with the reference input supply - reference noise directly couples into output jitter.
Do not assume the SI5345A-D04313-GM will boot with default register settings - the suffix D04313 denotes a factory NVM image that requires the correct ClockBuilder Pro project file for re-programming if NVM is ever erased. Loss-of-lock (LOL) at first power-up usually indicates a missing or wrong reference input; check INx/INxb differential swing and DC-bias levels against the datasheet before debugging PLL parameters.
Compliance-Informationen
RoHS and lead-free per Skyworks product page (LMY/ZQKI G-suffix indicates matte-tin Pb-free). Operating temperature range and halogen-free status were not present in the verified web data and are noted as [DATA_NEEDED].
