TPS54120 - Low-Noise 1A DC-DC + LDO Supply | TI
Teilenummer: TPS54120RGYR ✓ Aktiv| Menge | Stückpreis | Gesamt |
|---|---|---|
| 1 | $6.1 | $6,10 |
| 10 | $5.49 | $54,90 |
| 100 | $4.72 | $472,00 |
| 500 | $4.1 | $2.050,00 |
| 1.000 | $3.66 | $3.660,00 |
TPS54120RGYR Übersicht
A power supply with an integrated DC-DC converter and LDO is a hybrid power management architecture within the voltage regulator family of power management ICs: the buck converter performs efficient step-down conversion, while the downstream LDO provides high power-supply rejection (PSR) and low output noise for sensitive loads. This two-stage approach in one IC eliminates the discrete two-chip design effort and is essential for powering clocking distribution, data converters, and RF circuits.
Key features include adjustable output voltage up to 6.0V via external resistors, soft-start, switching-frequency synchronization to an external clock, spread-spectrum clocking (SSC) for EMI reduction, power-good output, output discharge, fixed UVLO, overcurrent protection, and synchronous rectification. The fully configurable converter and LDO allow a wide range of low-noise rail designs from a single device.
Architecturally, the proprietary interaction between the buck stage and the LDO optimizes the efficiency-versus-noise trade-off: the converter handles the bulk voltage transformation, keeping LDO dropout small so PSR remains high with minimal efficiency penalty. The 24-VQFN (RGY) package provides a compact footprint with good thermal performance for space-constrained designs.
Typical applications include telecom infrastructure, pico and femto base stations, and powering sensitive clocking distribution such as PLLs, VCOs, and high-speed ADCs and DACs, where clean rails directly improve phase noise and SNR.
Design tip: keep the switching node short to minimize EMI, bypass the LDO output with a low-ESR ceramic capacitor for stability, and use the soft-start pin to control inrush current at power-up. Prices referenced are as of 2026-08-29.
Drop-in-Alternativen für TPS54120RGYR – gleiches Gehäuse, Pin-kompatibel. Bauteile mit anderem Gehäuse, die eine PCB-Überarbeitung erfordern, sind ausgeschlossen.
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Für dieses Produkt sind keine Drop-in-Alternativen verfügbar.
Alternativen anfordernTPS54120RGYR Grenzwerte & elektrische Eigenschaften
| Topologie | Step-Down (Buck) DC-DC + Linear (LDO) |
| Anzahl der Ausgänge | 2 |
| Eingangsspannungsbereich | 4.5 V to 17 V |
| Ausgangsspannungsbereich | Adjustable up to 6.0 V |
| Output Current | 1 A |
| Schaltfrequenz | 200 kHz to 1.2 MHz |
| Synchrongleichrichtung | Yes |
| Sanftanlauf | Adjustable |
| Frequency Synchronization | Yes |
| Spread-Spectrum Clocking (SSC) | Yes |
| Protection Features | Overcurrent, fixed UVLO |
| Steuerungseigenschaften | Enable, Power Good, Output Discharge |
| Gehäuse | 24-VQFN (5.5 x 3.5 mm) |
| Montageart | Surface Mount |
| RoHS-Status | Compliant |
TPS54120RGYR Pin-Konfiguration
| Pin 1 | BOOT — Bootstrap for high-side gate driver |
| Pin 2 | PH — Switching node of buck converter |
| Pin 3 | VIN — Input supply, 4.5V to 17V |
| Pin 4 | EN — Enable input |
| Pin 5 | SS/TR — Soft-start / tracking |
| Pin 6 | RT/CLK — Frequency setting / external clock sync |
| Pin 7 | PGND — Power ground |
| Pin 8 | VSENSE — Buck feedback voltage sense |
| Pin 9 | PWRGD — Power-good open-drain output |
| Pin 10 | LDOIN — LDO input from converter output |
| Pin 11 | LDOOUT — LDO regulated output |
| Pin 12 | AGND — Analog ground |
Typische Anwendungen
TPS54120RGYR ist geeignet für 6 Anwendungs: Telecom Infrastructure Power, Pico and Femto Base Stations, Clocking Distribution (PLL/VCO), High-Speed ADC/DAC Analog Rails, Industrial 12V Bus Point-of-Load, Test and Measurement Instruments.
Telecom Infrastructure Power
The TPS54120 fits telecom infrastructure rails because its 4.5V to 17V input directly accepts 12V distributed bus voltages while delivering a regulated, low-noise output up to 6.0V at 1A. The integrated buck plus high-PSR LDO architecture suppresses switching ripple so downstream line cards and clock circuits see a clean supply. Spread-spectrum clocking and 200kHz to 1.2MHz frequency synchronization help the system pass EMC requirements in dense chassis environments.
Empfohlen
Pico and Femto Base Stations
In pico and femto base stations, board area and noise are both critical. The TPS54120 consolidates a buck converter and LDO into a single 24-VQFN (5.5x3.5 mm) footprint, cutting BOM count versus a discrete two-chip solution. Its high power-supply rejection keeps the local oscillator and transceiver supply quiet, while fixed UVLO and overcurrent protection add robustness for outdoor small-cell hardware running from 12V feeds.
Empfohlen
Clocking Distribution (PLL/VCO)
The TPS54120 is explicitly targeted at powering sensitive clocking distribution such as PLLs and VCOs. The LDO stage rejects ripple from the internal synchronous buck, so phase-noise degradation from supply modulation is minimized - directly improving jitter performance. Adjustable output up to 6.0V supports common clock-IC core voltages, and the power-good pin enables rail monitoring in redundant clock trees. Frequency synchronization keeps the switching tone out of sensitive measurement bands.
Empfohlen
High-Speed ADC/DAC Analog Rails
High-speed data converters require analog supply rails with low noise and high PSR to preserve SNR. The TPS54120 supplies up to 1A at up to 6.0V with the LDO stage filtering the buck ripple, providing the clean AVDD rail converters need. Bypassing the LDO output with low-ESR ceramic capacitors maintains stability and low output impedance across the converter's sampling bandwidth. The compact VQFN-24 keeps the supply close to the converter.
Empfohlen
Industrial 12V Bus Point-of-Load
The TPS54120's 4.5V to 17V input range accommodates industrial 12V buses with tolerance for transients, making it a compact point-of-load supply for PLC I/O, sensors, and mixed-signal boards. Synchronous rectification improves light-load efficiency, and adjustable soft-start controls inrush on shared rails. Overcurrent protection and output discharge simplify fault handling in multi-rail industrial systems where controlled shutdown sequencing matters.
Empfohlen
Test and Measurement Instruments
Bench instruments and modules need quiet local supplies near clock oscillators and precision analog front ends. The TPS54120 provides a single-IC solution: the buck stage handles efficient step-down from 12V, while the high-PSR LDO delivers the low-noise rail that keeps spectrum-analyzer-grade signal chains free of spurs. Adjustable switching frequency allows designers to place residual switching tones outside the instrument's measurement bands.
Empfohlen
Zusammenfassung der empfohlenen Produkte
Technische Referenzdaten für TPS54120RGYR – Vergleich, Designhinweise und Compliance-Informationen.
Auswahlhilfe
Vergleich mit Alternativen
| Parameter | Dieses Produkt | TPS62912 | TPS54620 | TPS74801QDRCRQ1 |
|---|---|---|---|---|
| Package | 24-VQFN (5.5x3.5 mm) | SOT-583 (DRL) | SOIC-8 (D) | VQFN-24 (DRC) |
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Architecture | Buck + LDO integrated | Buck only | Buck only | LDO only |
| Output Voltage | Adjustable up to 6.0 V | Adjustable/Fixed | Adjustable to 6 V | Adjustable, up to 15 V |
| SSC / Sync | Yes | Yes | Sync only | N/A |
| Drop-in Replacement | - | No (redesign + external LDO) | No (needs external LDO) | No (LDO only) |
Wichtigste Unterscheidungsmerkmale
- Single-IC buck + LDO integration (vs. TPS62912)
- 200kHz-1.2MHz adjustable frequency with SSC (vs. TPS54620)
- Compact 5.5x3.5 mm VQFN-24 for a complete two-stage supply (vs. TPS74801QDRCRQ1)
Designhinweise
Keep the PH switching node and BOOT capacitor connections as short and compact as possible to minimize EMI and parasitic ringing. Place VIN decoupling ceramic capacitors within 2-3 mm of the VIN pin, and route the power ground (PGND) return directly under the switching loop. Use the exposed pad as the main thermal and ground connection with a solid via array to the ground plane.
Bypass the LDO output with a low-ESR ceramic capacitor per the datasheet's stability requirements to ensure loop stability and low output impedance. Set the soft-start capacitor to limit inrush on shared 12V rails, and use the adjustable RT/CLK resistor to place the switching frequency away from sensitive RF bands or synchronize to a system clock.
Do not exceed 17V input - the device is intended for 12V buses with limited headroom, not wide Vin applications. Verify the LDO input-to-output headroom: if the buck output is set too close to the LDO output, PSR degrades. Ensure the output divider uses 1% or better resistors to keep the adjustable output within the 6.0V maximum.
Compliance-Informationen
RoHS compliant per TI product listing. AEC-Q100 qualification not indicated for this part in the provided data.
