TPS544B20RVFR - 18V, 20A Sync Buck Converter | Texas Instruments
Teilenummer: TPS544B20RVFR ✓ Aktiv| Menge | Stückpreis | Gesamt |
|---|---|---|
| 1 | $8.2 | $8,20 |
| 10 | $7.4 | $74,00 |
| 100 | $6.65 | $665,00 |
| 500 | $6.05 | $3.025,00 |
| 1.000 | $5.55 | $5.550,00 |
| 2.500 | $5.1 | $12.750,00 |
TPS544B20RVFR Übersicht
A buck converter is a switch-mode DC-DC topology that steps a higher input voltage down to a lower regulated output by rapidly switching an inductive element and rectifying the result through synchronous MOSFETs. Compared to linear regulators, buck converters reach efficiencies in the high-90% region at moderate duty ratios, making them the workhorse of point-of-load conversion for FPGAs, ASICs, DSPs, and server rails. The 5 mm × 7 mm integrated-FET footprint seen on the TPS544B20 family pushed the power-density envelope well above what discrete controllers could deliver at the same footprint.
Key datasheet specifications for the TPS544B20 include 20-A continuous output, 4.5-V to 18-V input, 0.6-V to ~5.5-V adjustable output, internal low-side and high-side MOSFETs, adaptive on-time D-CAP3 control, and selectable soft-start with PMBus-readable VIN/VOUT/IOUT/Temperature. Protection features include OVP, UVLO, OCP, OTP, and pre-bias safe startup; the device also supports margining and sequencing through PMBus commands.
The part is built on TI's stacked-die / copper-clip LQFN-CLIP package, which lowers the silicon-to-PCB thermal path to roughly 14 C/W (θ_JC) on the top clip and about 17 C/W (θ_JB) on the bottom pad. This enables sustained 20-A operation with a properly laid-out 4-layer PCB and minimal airflow, while remaining small enough for space-constrained telecom, server, and storage cards.
Typical applications include 12-V-input point-of-load conversion for telecom and networking ASICs, FPGA core and transceiver rails, server and storage auxiliary rails, industrial point-of-use 5-V or 3.3-V generation, and digital power-system designs that exploit the PMBus interface for adaptive voltage scaling and telemetry-driven health monitoring.
When designing with this part, allocate at least four PCB layers for the 20-A current path and follow the datasheet's decoupling, inductor, and bootstrap layout guidance. Because the LQFN-CLIP pad is the dominant thermal path, generous copper pour and thermal vias directly under the exposed pad are critical; without them the part will derate quickly above ~15 A.
This page synthesizes the official TPS544B20 datasheet, current distributor pricing, drop-in same-brand and cross-brand alternatives, and practical layout/thermal guidance not found in a single manufacturer document.
Drop-in-Alternativen für TPS544B20RVFR – gleiches Gehäuse, Pin-kompatibel. Bauteile mit anderem Gehäuse, die eine PCB-Überarbeitung erfordern, sind ausgeschlossen.
Varianten dieser Serie
Modelle derselben Serie, die drop-in-kompatibel sind mit TPS544B20RVFR (gleiche Bauform und Footprint) – abweichend in Digital Interface, Package, Mounting Type, Output Voltage Range, Topology.
Schnellvergleichstool – Wählen Sie Alternativbauteile für den Direktvergleich:
TPS544C20RVFR
✅ Drop-In✓ Auf Lager
$5.21 / Stück
Datenblatt ansehen →TPS544B20RVFT
✅ Drop-In📋 Referenzalternative (nicht im Katalog)
TPS544A28RSLR
✅ Drop-In📋 Referenzalternative (nicht im Katalog)
TPS546C20RVFR
✅ Drop-In📋 Referenzalternative (nicht im Katalog)
TPS543B20RVFR
✅ Drop-In ⚠️ Spezifikationen ungeprüft📋 Referenzalternative (nicht im Katalog)
TPS544B20RVFR Grenzwerte & elektrische Eigenschaften
| Topologie | Synchronous Buck (Step-Down) |
| Eingangsspannungsbereich | 4.5 V to 18 V |
| Ausgangsspannungsbereich | 0.6 V to 5.5 V (adjustable) |
| Continuous Output Current | 20 A |
| Schaltfrequenz | Selectable / external RT (typical 500 kHz - 1 MHz range) |
| Control Architecture | D-CAP3 adaptive on-time with PMBus |
| MOSFETs | Internal high-side and low-side (integrated FETs) |
| Digital Interface | PMBus (SMBus-compatible) for telemetry, margining, sequencing, fault reporting |
| Sanftanlauf | Programmable via PMBus / SS pin |
| Betriebstemperaturbereich | -40 C to +125 C junction |
| Gehäuse | 40-pin LQFN-CLIP (RVF), 5 mm x 7 mm |
| Montageart | Surface Mount |
| MSL-Level | 3 (per JEDEC J-STD-020) |
| RoHS-Status | Compliant |
| Protections | OVP, UVLO, OCP (cycle-by-cycle), OTP, pre-bias safe startup |
| PMBus Address Strapping | Resistor-programmable |
TPS544B20RVFR Pin-Konfiguration
| Pin 1 | PGND — Power ground (low-side FET return) |
| Pin 2 | PVIN — Power input voltage (4.5 V to 18 V) |
| Pin 3 | PGND — Power ground (low-side FET return) |
| Pin 4 | PVIN — Power input voltage (4.5 V to 18 V) |
| Pin 5 | BOOT — Bootstrap capacitor for high-side gate driver |
| Pin 6 | SW — Switching node (high-side drain / low-side source) |
| Pin 7 | SW — Switching node |
| Pin 8 | SW — Switching node |
| Pin 9 | PGND — Power ground |
| Pin 10 | VOUT — Output voltage sense / power stage output |
| Pin 11 | VOUT — Output voltage sense |
| Pin 12 | VOUT — Output voltage sense |
| Pin 13 | VOUT — Output voltage sense |
| Pin 14 | VOUT — Output voltage sense |
| Pin 15 | VOUT — Output voltage sense |
| Pin 16 | PGND — Power ground |
| Pin 17 | PGND — Power ground |
| Pin 18 | PGND — Power ground |
| Pin 19 | PVIN — Power input voltage |
| Pin 20 | PVIN — Power input voltage |
| Pin 21 | PVCC — Internal 5 V regulator bypass / decoupling |
| Pin 22 | NC — Not connected (per datasheet) |
| Pin 23 | NC — Not connected (per datasheet) |
| Pin 24 | AGND — Analog ground (return for sensitive analog circuits) |
| Pin 25 | FB — Feedback (output voltage divider sense, 0.6 V reference) |
| Pin 26 | COMP — Compensation network connection |
| Pin 27 | RT/SS — Switching-frequency resistor / soft-start programming |
| Pin 28 | EN — Enable (logic-level, programmable UVLO) |
| Pin 29 | PGOOD — Power-good indicator (open-drain output) |
| Pin 30 | ALERT — PMBus ALERT (open-drain) |
| Pin 31 | SDA — PMBus data (open-drain, requires external pull-up) |
| Pin 32 | SCL — PMBus clock (open-drain, requires external pull-up) |
| Pin 33 | ADDR — PMBus address selection (resistor-programmable) |
| Pin 34 | VREF — Reference voltage bypass (decoupling point) |
| Pin 35 | PVCC — Internal 5 V regulator bypass |
| Pin 36 | NC — Not connected (per datasheet) |
| Pin 37 | NC — Not connected (per datasheet) |
| Pin 38 | NC — Not connected (per datasheet) |
| Pin 39 | NC — Not connected (per datasheet) |
| Pin 40 | NC — Not connected (per datasheet) |
Typische Anwendungen
TPS544B20RVFR ist geeignet für 7 Anwendungs: FPGA Core and Transceiver POL Rails, Server and Storage 12 V Intermediate Bus Conversion, Telecom and Networking ASIC Power, Industrial 24 V / 12 V Point-of-Use Conversion, DSP/Microprocessor Power Rails, Digital Power Systems with PMBus Telemetry, Test and Measurement Equipment Rails.
FPGA Core and Transceiver POL Rails
The TPS544B20RVFR's 0.6 V to 5.5 V adjustable output covers both modern FPGA core rails (0.85 V, 0.9 V, 1.0 V, 1.2 V) and the 1.8 V/2.5 V/3.3 V auxiliary levels, all from a 4.5 V - 18 V bus. Its 20 A continuous rating supports a multi-rail FPGA on a single converter, while D-CAP3 control delivers the fast transient response transceivers demand on the MGT supply. The PMBus interface enables adaptive voltage scaling without external DAC circuitry, a hard requirement for many high-end FPGAs and SoCs.
Empfohlen
Server and Storage 12 V Intermediate Bus Conversion
Inside modern server and storage cards, 12 V backplane power is stepped down locally to feed ASIC controllers, DDR termination rails, and point-of-use loads. The TPS544B20RVFR handles 4.5 V to 18 V input directly from that 12 V bus and supplies 20 A continuous at adjustable output - enough to power a controller chip, hot-swap controller, and surrounding logic. PMBus telemetry feeds health monitoring and predictive maintenance stacks common in datacenter platforms.
Empfohlen
Telecom and Networking ASIC Power
Telecom line cards and networking ASICs require clean, high-current point-of-load supplies with PMBus observability for thermal and fault telemetry into the chassis management controller. The TPS544B20RVFR's integrated FETs, 4.5-18 V input, 0.6-5.5 V adjustable output, and rich PMBus command set fit directly into a -48 V to 12 V brick-fed system. Its D-CAP3 control keeps dynamic impedance low enough for heavy ASIC load-step transients.
Empfohlen
Industrial 24 V / 12 V Point-of-Use Conversion
Factory automation and PLC systems commonly run on 12 V or 24 V industrial bus rails that need to be stepped down to 5 V, 3.3 V, or 1.8 V for controller and sensor power. The TPS544B20RVFR's 18 V upper VIN gives margin above 12 V nominals (handling spikes up to 18 V) while still operating comfortably down to 4.5 V during low-line events. The integrated protection features (OVP, UVLO, OCP, OTP) suit harsh industrial environments where sustained fault tolerance is required.
Empfohlen
DSP/Microprocessor Power Rails
TI C6000-series DSPs, Sitara ARM processors, and similar microprocessors need low-voltage, high-current rails with adaptive voltage scaling. The TPS544B20RVFR's 0.6 V reference, 20 A rating, and PMBus-based output-voltage control are a direct match for core rails around 0.9-1.2 V. D-CAP3 control reduces output capacitor count compared to traditional voltage-mode converters and helps the design pass DSP transient-load requirements with fewer components.
Empfohlen
Digital Power Systems with PMBus Telemetry
Where digital power system management matters - blade servers, ATCA/AdvancedTCA cards, base stations, and high-end industrial controllers - the TPS544B20RVFR's PMBus telemetry (VIN, VOUT, IOUT, temperature, fault flags) and configuration surface cleanly fit a closed-loop platform manager. The chip supports sequencing, margining, and fault-masking commands, eliminating many external GPIO expanders and DAC channels in the overall power tree design.
Empfohlen
Test and Measurement Equipment Rails
Bench instruments and modular test equipment demand clean, programmable, and well-instrumented rails to bias analog front-ends, DACs, and high-speed ADCs. The TPS544B20RVFR's low output noise, PMBus programmability, and ability to sit on a 4.5-18 V input make it attractive for the LDO-follower post-regulation stage and as the primary rail for digital controllers inside the chassis. TI's datasheet reference designs simplify certification of the final test platform.
Empfohlen
Zusammenfassung der empfohlenen Produkte
Technische Referenzdaten für TPS544B20RVFR – Vergleich, Designhinweise und Compliance-Informationen.
Auswahlhilfe
Vergleich mit Alternativen
| Parameter | Dieses Produkt | TPS544C20RVFR | TPS544B20RVFT | TPS544A28RSLR | TPS546C20RVFR | TPS543B20RVFR |
|---|---|---|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Package | LQFN-CLIP-40 (RVF) 5x7 mm | LQFN-CLIP-40 (RVF) 5x7 mm - same | LQFN-CLIP-40 (RVF) 5x7 mm - same | LQFN-CLIP-40 (RVF) - same | LQFN-CLIP-40 (RVF) - same | LQFN-CLIP-40 (RVF) - same |
| Input Voltage Range | 4.5 V to 18 V | 4.5 V to 18 V | 4.5 V to 18 V | 4.5 V to 18 V | 4.5 V to 18 V | 4.5 V to 18 V |
| Output Voltage Adjustable Range | 0.6 V to 5.5 V | 0.6 V to 5.5 V | 0.6 V to 5.5 V | 0.6 V to 5.5 V | 0.6 V to 5.5 V | 0.6 V to 5.5 V |
| Control Architecture | D-CAP3 (adaptive on-time) | D-CAP3 | D-CAP3 | D-CAP4 (advanced) | D-CAP3 | D-CAP2/D-CAP3 |
| PMBus Interface | Yes (full telemetry + control) | Yes | Yes | Yes | Yes | Yes |
| Internal MOSFETs | Yes (integrated high-side + low-side) | Yes | Yes | Yes | Yes | Yes |
| Drop-in Footprint Compatibility | Reference | Same RVF 40-pin LQFN-CLIP, pin-compatible | Same RVF 40-pin LQFN-CLIP, identical die | Same RVF 40-pin LQFN-CLIP, may need FB/PGOOD recheck | Same RVF 40-pin LQFN-CLIP, pin-compatible | Same RVF 40-pin LQFN-CLIP, lower current |
Wichtigste Unterscheidungsmerkmale
- Established 20 A tier with mature TI software/driver stack (vs. TPS544C20RVFR)
- Immediate 20 A continuous rating without firmware/pinout rework (vs. TPS544A28RSLR)
- Optimized for 12 V bus point-of-load conversion (vs. TPS546C20RVFR)
- Pin-compatible upgrade path within the same LQFN-CLIP family (vs. TPS543B20RVFR)
Designhinweise
Estimated: at 12 VIN, 3.3 VOUT, and a 20 A continuous load, the converter dissipates roughly (12 - 3.3) x 20 x (1 - efficiency)/efficiency watts - on the order of 16 W at 90% efficiency, 26 W at 80%. The LQFN-CLIP (RVF) package relies primarily on the bottom exposed pad (θJB about 17 C/W per the TI datasheet thermal table) for heat extraction. The PCB must include a 4-layer stack-up with the top-layer copper poured to a generous area (at least 1 square inch) over the LQFN-CLIP pad, and arrays of thermal vias connecting the exposed pad to inner copper planes. Without these, the part derates well below 20 A in still air.
Place PVIN input ceramic capacitors as close to the PVIN/PGND pins as possible to minimize the high-frequency loop area of the 20 A switching current. Use a 1 x 22 uF + 2 x 47 uF ceramic bank on PVIN per the TI reference design, plus a 1 x 4.7 uF BOOT capacitor between BOOT and SW. Keep the SW copper area compact to limit radiated EMI; route the FB and PMBus traces away from SW and the BOOT switching node to avoid noise coupling into the analog reference.
The 40-pin LQFN-CLIP (RVF) layout requires inter-digitated PVIN/VOUT/SW/PGND on top copper with wide traces to carry 20 A. Keep the VOUT sense trace short and Kelvin-connected back to the load, not to the inductor pad. Place the SCL/SDA pull-up resistors and PMBus capacitors near the IC; route PMBus traces away from the SW node and shield them with a ground guard ring if possible to maintain clean digital signal integrity.
Do not bypass the SS (soft-start) capacitor - omitting it leads to large inrush currents that can trigger OCP at startup. Set the ADDR resistor to the correct PMBus address before applying power, since changing it after first power-up requires a re-strap or PMBus command. Do not exceed 18 V on PVIN; 12 V busses regularly see 14-16 V transients from inductive loads, so leave at least 2 V margin. Confirm inductor saturation current is at least 50% above nominal load (>= 30 A saturation) to handle transients.
Estimated: at 12 VIN to 1.0 VOUT at 20 A, the converter sees a duty ratio of approximately 8.3% and must handle a peak inductor current of at least 30 A (load + 50% ripple margin). Output-ripple target of 1% of VOUT (10 mV) requires a minimum output capacitance of roughly CV ripple / (8 f x 1% VOUT). Select a 2-stage ceramic bank (e.g., 4 x 22 uF/X7R/1210 plus 1 x 220 uF/polymer) to maintain ripple within spec and absorb fast load steps of 5 A / 10 us.
Compliance-Informationen
RoHS-compliant per TI product folder; not AEC-Q100 qualified - the part targets telecom/server/computing, not automotive. Halogen-free and lead-free per TI's LQFN-CLIP family materials declaration.
