ATSAMA5D26A-CUR vs ATSAMA5D26B-CN Comparación
Comparación detallada lado a lado de ATSAMA5D26A-CUR por Microchip Technology y ATSAMA5D26B-CN por Microchip Technology. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Microchip Technology
ATSAMA5D26A-CUR - 500MHz Cortex-A5 MPU, 289-LFBGA | Microchip
ATSAMA5D26A-CUR ✓ ActivoMicrochip Technology
ATSAMA5D26B-CN - ARM Cortex-A5 MPU 500MHz | Microchip | 289-LFBGA
ATSAMA5D26B-CN ✓ ActivoComparación de especificaciones
| Parámetro | ATSAMA5D26A-CUR | ATSAMA5D26B-CN |
|---|---|---|
| Marca | Microchip Technology | Microchip Technology |
| Categoría | Microcontrollers | Microcontrollers |
| Estado del ciclo de vida | Activo | Activo |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $14,20 | $13,05 |
| Core Architecture | ARM Cortex-A5 (ARMv7-A) | ARM Cortex-A5 (Armv7-A) |
| Maximum CPU Clock | 500 MHz | — |
| Core Count | 1 | — |
| Bit Width | 32-bit | — |
| Internal SRAM | 128 KB | — |
| Internal ROM | 160 KB | — |
| L1 Instruction Cache | 32 KB | 32 kbyte |
| L1 Data Cache | 32 KB | 32 kbyte |
| FPU / NEON | Yes (single-precision FPU + NEON) | — |
| Memory Interfaces | DDR2, DDR3L, LPDDR2, LPDDR3, QSPI, e.MMC, NAND, NOR | — |
| External Memory Bus | 16-bit EBI | — |
| Display Controller | Integrated LCD controller up to WXGA (1366x768) | — |
| Ethernet | 2x 10/100 Mbps EMAC (GMII/RGMII/MII) | — |
| USB | 2x USB 2.0 High-Speed Host + 1x USB 2.0 Device/Host | — |
| CAN | 2x CAN-FD | — |
| Crypto Accelerator | AES, SHA, TRNG, secure boot | — |
| ADC | 12-bit, 1 Msps, up to 12 channels | — |
| Encapsulado | 289-LFBGA, 14x14 mm, 0.8 mm pitch | 289-LFBGA (14x14 mm) |
| Supply Voltage (Core) | 1.2 V (typ) | — |
| Temperatura de funcionamiento | -40C to +85C (Industrial) | — |
| Tipo de montaje | Surface Mount | Surface Mount |
| Nivel MSL | 3 (per JEDEC J-STD-020) | [DATA_NEEDED: MSL level] |
| Estado RoHS | Compliant | Compliant |
| Number of Cores | — | 1 |
| Frecuencia de reloj máxima | — | 500 MHz |
| L2 Cache | — | 128 kbyte (configurable as SRAM) |
| Memory Management Unit | — | Yes (MMU) |
| NEON Media Processing Engine | — | Yes |
| Arm TrustZone | — | Yes |
| ETM/ETB Support | — | Yes |
| DDR Memory Interface | — | DDR2, DDR3L, LPDDR2, LPDDR3 |
| Flash Memory Interface | — | QSPI, e.MMC |
| Backup Mode Current | — | 5 uA |
| Security Features | — | Secure boot, AES, SHA, TRNG, tamper pins |
| Peripheral Interfaces | — | I2C, SPI, USART, UART, QSPI, CAN, HSIC, SMC |
| Embedded Audio Subsystem | — | Yes |
| Ball Pitch | — | 0.8 mm |
| Rango de temperatura de funcionamiento | — | -40C to +85C (industrial, -CN grade) |