CDK8307AILP64 vs CDK8307CILP64 Comparación
Comparación detallada lado a lado de CDK8307AILP64 por MaxLinear y CDK8307CILP64 por MaxLinear. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
MaxLinear
CDK8307AILP64 - 12/13-bit Octal Ultra-Low Power LVDS ADC | MaxLinear
CDK8307AILP64 ✓ ActivoMaxLinear
CDK8307CILP64 - 12/13-bit 65MSPS Octal ADC, LVDS Output | MaxLinear
CDK8307CILP64 ✓ ActivoComparación de especificaciones
| Parámetro | CDK8307AILP64 | CDK8307CILP64 |
|---|---|---|
| Marca | MaxLinear | MaxLinear |
| Categoría | ADC/DAC | ADC/DAC |
| Estado del ciclo de vida | Activo | Activo |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $18,45 | $11,95 |
| Resolución | 12/13-bit (selectable) | 12/13-bit (selectable) |
| Number of Channels | 8 (simultaneous sampling) | 8 (simultaneous sampling) |
| Sample Rate Range | 20 / 40 / 50 / 65 / 80 MSPS | — |
| Architecture | Pipelined ADC with proprietary core | Proprietary pipeline ADC |
| Output Interface | Serial LVDS | — |
| Reference | Internal reference (integrated) | Internal (integrated bandgap) |
| Tensión de alimentación | [DATA_NEEDED: supply voltage] | — |
| Power Dissipation (Typ) | Ultra-low power (per-channel shutdown) | — |
| Shutdown Modes | Per-channel + full-chip idle (via external pin) | — |
| Control Interface | Serial programming interface (SPI-style) | SPI-compatible serial |
| FPGA Compatibility | Designed to interface with major FPGA vendors | — |
| Encapsulado | 64-pin QFN (ILP64) | 64-pin LQFP (LP64) |
| Tipo de montaje | Surface Mount | Surface Mount |
| Rango de temperatura de funcionamiento | [DATA_NEEDED: temperature range] | [DATA_NEEDED: operating temperature range] |
| Estado RoHS | Compliant | Compliant (per MaxLinear product page) |
| Original Brand | Cadeka / Exar (now MaxLinear) | — |
| Sample Rate | — | 65 MSPS maximum (20/40/50/65 MSPS grades) |
| Digital Output Interface | — | Serial LVDS |
| Input Type | — | Differential analog inputs |
| Power Profile | — | Ultra-low power (per-channel) |
| Supply Voltage (AVDD) | — | [DATA_NEEDED: AVDD nominal] |
| Supply Voltage (DRVDD/LVDS) | — | [DATA_NEEDED: DRVDD nominal] |
| ENOB | — | [DATA_NEEDED: effective number of bits] |
| SNR | — | [DATA_NEEDED: signal-to-noise ratio] |
| SFDR | — | [DATA_NEEDED: spurious-free dynamic range] |