EP1810JM-45 vs EP1810JC-45 Comparación
Comparación detallada lado a lado de EP1810JM-45 por Altera y EP1810JC-45 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP1810JM-45 | EP1810JC-45 |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | NRND |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $14,20 | $21,10 |
| Device Family | Classic EPLD (EP1810 series) | — |
| Macrocells | 48 | 48 |
| Usable Gates | ~900 gates | — |
| Propagation Delay (tpd) | 45 ns (max, -45 speed grade) | 45 ns |
| Supply Voltage (VCC) | 4.5 V to 5.5 V | — |
| Technology | CMOS, UV-EPROM configuration | CMOS, UV-erasable |
| Package Type | JLCC-68 (ceramic J-leaded chip carrier) | — |
| Package Code | JM (windowed ceramic, UV-erasable) | QCCJ |
| Recuento de pines | 68 | 68 |
| Temperatura de funcionamiento | -55 C to +125 C (military grade) | — |
| I/O Compatibility | CMOS / TTL | — |
| Configuration Method | JEDEC fuse map, EPROM programmer | — |
| Programming Technology | UV-erasable EPROM (non-volatile, instant-on) | — |
| Tipo de montaje | Surface Mount (J-lead) | Surface Mount |
| Logic Type | EPLD / PLD (programmable logic device) | — |
| Estado RoHS | [DATA_NEEDED: RoHS status - legacy mil-spec part] | [DATA_NEEDED: RoHS compliance not stated in verified data] |
| Nivel MSL | [DATA_NEEDED: MSL level] | — |
| Product Type | — | Classic EPLD (Erasable Programmable Logic Device) |
| Family | — | EP1810 (Classic EPLD Family) |
| Equivalent Gates | — | 2100 gates |
| Dedicated Inputs | — | 12 |
| I/O Pins | — | 48 |
| Total User I/O | — | 60 |
| Frecuencia de reloj máxima | — | 33.3 MHz |
| Maximum Supply Voltage | — | 5.25 V |
| Encapsulado | — | PLCC-68 (QCCJ, J-Lead, windowed ceramic) |
| Temperature Grade | — | Commercial |