EP1810JM-45 vs EP1810JC-45 对比
详细并排对比 EP1810JM-45 出自 Altera 和 EP1810JC-45 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EP1810JM-45 | EP1810JC-45 |
|---|---|---|
| 品牌 | Altera | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | 不推荐新设计 |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $14.20 | $21.10 |
| Device Family | Classic EPLD (EP1810 series) | — |
| Macrocells | 48 | 48 |
| Usable Gates | ~900 gates | — |
| Propagation Delay (tpd) | 45 ns (max, -45 speed grade) | 45 ns |
| Supply Voltage (VCC) | 4.5 V to 5.5 V | — |
| Technology | CMOS, UV-EPROM configuration | CMOS, UV-erasable |
| Package Type | JLCC-68 (ceramic J-leaded chip carrier) | — |
| Package Code | JM (windowed ceramic, UV-erasable) | QCCJ |
| 引脚数量 | 68 | 68 |
| 工作温度 | -55 C to +125 C (military grade) | — |
| I/O Compatibility | CMOS / TTL | — |
| Configuration Method | JEDEC fuse map, EPROM programmer | — |
| Programming Technology | UV-erasable EPROM (non-volatile, instant-on) | — |
| 安装类型 | Surface Mount (J-lead) | Surface Mount |
| Logic Type | EPLD / PLD (programmable logic device) | — |
| RoHS 状态 | [DATA_NEEDED: RoHS status - legacy mil-spec part] | [DATA_NEEDED: RoHS compliance not stated in verified data] |
| MSL 等级 | [DATA_NEEDED: MSL level] | — |
| Product Type | — | Classic EPLD (Erasable Programmable Logic Device) |
| Family | — | EP1810 (Classic EPLD Family) |
| Equivalent Gates | — | 2100 gates |
| Dedicated Inputs | — | 12 |
| I/O Pins | — | 48 |
| Total User I/O | — | 60 |
| 最大时钟频率 | — | 33.3 MHz |
| Maximum Supply Voltage | — | 5.25 V |
| 封装 | — | PLCC-68 (QCCJ, J-Lead, windowed ceramic) |
| Temperature Grade | — | Commercial |