EP1810LC-30 vs EP1810LC-20T Comparación
Comparación detallada lado a lado de EP1810LC-30 por Altera y EP1810LC-20T por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP1810LC-30 | EP1810LC-20T |
|---|---|---|
| Marca | Altera | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $9,95 | $9,95 |
| Product Type | Classic EPLD (Erasable Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Family | Altera Classic EPLD | Altera Classic EPLD |
| Macrocells | 48 | 48 |
| Flip-Flops | 48 (one per macrocell) | — |
| Speed Grade (tPD) | 30 ns | — |
| Tensión de alimentación | 5 V (typical) | — |
| Technology | CMOS, low-power (LC) | — |
| Encapsulado | JLCC-68 (68-pin J-Lead ceramic chip carrier) | — |
| Programming | Device programmer or JTAG | — |
| Temperatura de funcionamiento | [DATA_NEEDED: temperature grade] | 0C to +70C (commercial) |
| Standby Current | [DATA_NEEDED: ICC standby] | — |
| Número de pines | 68 | — |
| Number of I/O Pins | [DATA_NEEDED: I/O count] | — |
| Logic Blocks | 48 macrocells | — |
| Estado RoHS | unknown (legacy ceramic package) | Non-compliant (legacy 5V PLCC) |
| Usable Gates | — | 900 gates |
| Logic Array Blocks (LABs) | — | 4 x 12 macrocells |
| Maximum Toggle Frequency | — | 50 MHz |
| Pin-to-Pin Logic Delay (tPD) | — | 20 ns |
| Supply Voltage (VCC) | — | 5 V |
| Package Type | — | PLCC-68 (J-lead) |
| Tipo de montaje | — | Surface Mount (socket-compatible) |
| Configuration Memory | — | On-chip EEPROM (non-volatile) |
| Programming Interface | — | JTAG (IEEE 1149.1) and Altera Master/Slave serial |
| Shipping Format | — | Tape & Reel ("T" suffix) |