EP1810LC-30 vs EP1810LC-20T 对比
详细并排对比 EP1810LC-30 出自 Altera 和 EP1810LC-20T 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EP1810LC-30 | EP1810LC-20T |
|---|---|---|
| 品牌 | Altera | Intel |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $9.95 | $9.95 |
| Product Type | Classic EPLD (Erasable Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Family | Altera Classic EPLD | Altera Classic EPLD |
| Macrocells | 48 | 48 |
| Flip-Flops | 48 (one per macrocell) | — |
| Speed Grade (tPD) | 30 ns | — |
| 电源电压 | 5 V (typical) | — |
| Technology | CMOS, low-power (LC) | — |
| 封装 | JLCC-68 (68-pin J-Lead ceramic chip carrier) | — |
| Programming | Device programmer or JTAG | — |
| 工作温度 | [DATA_NEEDED: temperature grade] | 0C to +70C (commercial) |
| Standby Current | [DATA_NEEDED: ICC standby] | — |
| 引脚数 | 68 | — |
| Number of I/O Pins | [DATA_NEEDED: I/O count] | — |
| Logic Blocks | 48 macrocells | — |
| RoHS 状态 | unknown (legacy ceramic package) | Non-compliant (legacy 5V PLCC) |
| Usable Gates | — | 900 gates |
| Logic Array Blocks (LABs) | — | 4 x 12 macrocells |
| Maximum Toggle Frequency | — | 50 MHz |
| Pin-to-Pin Logic Delay (tPD) | — | 20 ns |
| Supply Voltage (VCC) | — | 5 V |
| Package Type | — | PLCC-68 (J-lead) |
| 安装类型 | — | Surface Mount (socket-compatible) |
| Configuration Memory | — | On-chip EEPROM (non-volatile) |
| Programming Interface | — | JTAG (IEEE 1149.1) and Altera Master/Slave serial |
| Shipping Format | — | Tape & Reel ("T" suffix) |