EP1810LC-30 vs EP1810LC-35T Comparación
Comparación detallada lado a lado de EP1810LC-30 por Altera y EP1810LC-35T por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP1810LC-30 | EP1810LC-35T |
|---|---|---|
| Marca | Altera | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $9,95 | $115,20 |
| Product Type | Classic EPLD (Erasable Programmable Logic Device) | Erasable Programmable Logic Device (EPLD) |
| Family | Altera Classic EPLD | — |
| Macrocells | 48 | — |
| Flip-Flops | 48 (one per macrocell) | — |
| Speed Grade (tPD) | 30 ns | — |
| Tensión de alimentación | 5 V (typical) | — |
| Technology | CMOS, low-power (LC) | CMOS |
| Encapsulado | JLCC-68 (68-pin J-Lead ceramic chip carrier) | 68-pin PLCC (Plastic Leaded Chip Carrier) |
| Programming | Device programmer or JTAG | — |
| Temperatura de funcionamiento | [DATA_NEEDED: temperature grade] | 0 C to +70 C (Commercial) |
| Standby Current | [DATA_NEEDED: ICC standby] | — |
| Número de pines | 68 | — |
| Number of I/O Pins | [DATA_NEEDED: I/O count] | — |
| Logic Blocks | 48 macrocells | — |
| Estado RoHS | unknown (legacy ceramic package) | Non-compliant (legacy PLCC product) |
| Device Family | — | EP1810 Classic EPLD |
| Usable Gates | — | 900 |
| Macro Cells | — | 48 |
| Pin-to-Pin Delay (tpd) | — | 35 ns |
| Maximum Frequency (fmax) | — | 28.6 MHz |
| Supply Voltage (Vcc) | — | 5 V |
| Logic Compatibility | — | 100% TTL emulation |
| Package Suffix | — | T = Tape and Reel |
| Tipo de montaje | — | Surface Mount (PLCC socket or direct solder) |
| Programming Method | — | UV-erasable (ceramic) / OTP (plastic); MAX+PLUS II |
| Logic Family Replacement Target | — | 74LS low-power Schottky TTL |