EP1810LC-30 vs EP1810LC-35T 비교
다음의 상세 나란히 비교: EP1810LC-30 제조: Altera 및 EP1810LC-35T 제조: Intel. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
사양 비교
| 파라미터 | EP1810LC-30 | EP1810LC-35T |
|---|---|---|
| 브랜드 | Altera | Intel |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | Obsolete | Obsolete |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $9.95 | $115.20 |
| Product Type | Classic EPLD (Erasable Programmable Logic Device) | Erasable Programmable Logic Device (EPLD) |
| Family | Altera Classic EPLD | — |
| Macrocells | 48 | — |
| Flip-Flops | 48 (one per macrocell) | — |
| Speed Grade (tPD) | 30 ns | — |
| 공급 전압 | 5 V (typical) | — |
| Technology | CMOS, low-power (LC) | CMOS |
| 패키지 | JLCC-68 (68-pin J-Lead ceramic chip carrier) | 68-pin PLCC (Plastic Leaded Chip Carrier) |
| Programming | Device programmer or JTAG | — |
| 동작 온도 | [DATA_NEEDED: temperature grade] | 0 C to +70 C (Commercial) |
| Standby Current | [DATA_NEEDED: ICC standby] | — |
| 핀 수 | 68 | — |
| Number of I/O Pins | [DATA_NEEDED: I/O count] | — |
| Logic Blocks | 48 macrocells | — |
| RoHS 상태 | unknown (legacy ceramic package) | Non-compliant (legacy PLCC product) |
| Device Family | — | EP1810 Classic EPLD |
| Usable Gates | — | 900 |
| Macro Cells | — | 48 |
| Pin-to-Pin Delay (tpd) | — | 35 ns |
| Maximum Frequency (fmax) | — | 28.6 MHz |
| Supply Voltage (Vcc) | — | 5 V |
| Logic Compatibility | — | 100% TTL emulation |
| Package Suffix | — | T = Tape and Reel |
| 실장 유형 | — | Surface Mount (PLCC socket or direct solder) |
| Programming Method | — | UV-erasable (ceramic) / OTP (plastic); MAX+PLUS II |
| Logic Family Replacement Target | — | 74LS low-power Schottky TTL |