EP1S20B672C7N vs EP1S20F672C7 Comparación
Comparación detallada lado a lado de EP1S20B672C7N por Intel y EP1S20F672C7 por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP1S20B672C7N | EP1S20F672C7 |
|---|---|---|
| Marca | Intel | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Última compra |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $320,00 | $195,00 |
| Series | Stratix | Stratix |
| Family | Stratix (original) | Altera Stratix FPGA |
| Process Technology | 0.13 µm CMOS | — |
| Logic Elements (LEs) | 18,460 | 18,460 |
| LABs / CLBs | 1,846 | — |
| Embedded Memory Bits | 1,669,248 bits | 1,669,248 |
| Maximum User I/O | 426 | — |
| Number of Pins / Balls | 672 | — |
| Package Type | 672-BBGA (Fine-pitch BGA, 35 × 35 mm, 1.27 mm pitch) | — |
| Supply Voltage (Core, VCCINT) | 1.5 V | — |
| Temperatura de funcionamiento | 0 °C to 85 °C (Commercial Extended) | 0C to 85C (commercial) |
| Speed Grade | -7 | C7 |
| Tipo de montaje | Surface Mount (BGA) | Surface Mount |
| Nivel MSL | 3 (per JEDEC J-STD-020) | [DATA_NEEDED: MSL level] |
| Logic Family | CMOS | CMOS, SRAM-based |
| Estado RoHS | [DATA_NEEDED: RoHS compliance] | unknown |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| User I/O Pins | — | 426 |
| DSP Blocks | — | [DATA_NEEDED: DSP block count] |
| Encapsulado | — | 672-ball FineLine BGA (35 x 35 mm, 1.27 mm pitch) |
| Core Supply Voltage | — | 1.5 V |
| Configuration Modes | — | JTAG, Passive Serial, Fast Passive Parallel, Active Serial |
| Clock PLLs | — | Up to 10 |