EP1S20B672C7N vs EP1S25F672C7N Comparación
Comparación detallada lado a lado de EP1S20B672C7N por Intel y EP1S25F672C7N por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP1S20B672C7N | EP1S25F672C7N |
|---|---|---|
| Marca | Intel | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $320,00 | $535,00 |
| Series | Stratix | — |
| Family | Stratix (original) | — |
| Process Technology | 0.13 µm CMOS | 0.13 µm CMOS |
| Logic Elements (LEs) | 18,460 | 25,660 |
| LABs / CLBs | 1,846 | — |
| Embedded Memory Bits | 1,669,248 bits | 1,944,576 |
| Maximum User I/O | 426 | 473 |
| Number of Pins / Balls | 672 | — |
| Package Type | 672-BBGA (Fine-pitch BGA, 35 × 35 mm, 1.27 mm pitch) | — |
| Supply Voltage (Core, VCCINT) | 1.5 V | — |
| Temperatura de funcionamiento | 0 °C to 85 °C (Commercial Extended) | 0 °C to 85 °C (commercial) |
| Speed Grade | -7 | — |
| Tipo de montaje | Surface Mount (BGA) | Surface Mount |
| Nivel MSL | 3 (per JEDEC J-STD-020) | [DATA_NEEDED: MSL rating] |
| Logic Family | CMOS | — |
| Estado RoHS | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: confirm from product page] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Device Family | — | Stratix |
| Logic Array Blocks (LABs) | — | 2,566 |
| Number of I/O Pins | — | 672 (BGA balls) |
| Encapsulado | — | 672-BBGA (FineLine BGA), 35 × 35 mm, 1.27 mm pitch |
| Core Supply Voltage (VCCINT) | — | 1.5 V |
| I/O Supply Voltage (VCCIO) | — | [DATA_NEEDED: bank-dependent 1.2 V–3.3 V] |
| Configuration Method | — | JTAG / Passive Serial / Active Serial |