EP1S20F672C7 vs EP1S20F672C7N Comparación
Comparación detallada lado a lado de EP1S20F672C7 por Intel y EP1S20F672C7N por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP1S20F672C7 | EP1S20F672C7N |
|---|---|---|
| Marca | Intel | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Última compra | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $195,00 | $109,20 |
| Series | Stratix | Stratix (first generation) |
| Family | Altera Stratix FPGA | Stratix |
| Logic Elements (LEs) | 18,460 | 18,460 |
| Embedded Memory Bits | 1,669,248 | — |
| User I/O Pins | 426 | — |
| DSP Blocks | [DATA_NEEDED: DSP block count] | 56 (dedicated 18x18 multipliers) |
| Encapsulado | 672-ball FineLine BGA (35 x 35 mm, 1.27 mm pitch) | 672-FBGA (FineLine BGA) |
| Logic Family | CMOS, SRAM-based | — |
| Core Supply Voltage | 1.5 V | — |
| Temperatura de funcionamiento | 0C to 85C (commercial) | 0°C to +85°C (commercial) |
| Speed Grade | C7 | C7 (-7) |
| Configuration Modes | JTAG, Passive Serial, Fast Passive Parallel, Active Serial | PS, PPS, FPP, JTAG |
| Tipo de montaje | Surface Mount | Surface Mount |
| Nivel MSL | [DATA_NEEDED: MSL level] | [DATA_NEEDED: moisture sensitivity level] |
| Estado RoHS | unknown | — |
| Clock PLLs | Up to 10 | — |
| Logic Cells | — | 18,460 |
| Configurable Logic Blocks (CLBs) | — | 2,132 |
| Embedded Memory (TriMatrix) | — | 1,669,248 bits (426 Kbit total) |
| Maximum User I/O | — | 586 |
| I/O Banks | — | [DATA_NEEDED: I/O bank count] |
| PLLs | — | Up to 12 |
| Maximum Operating Frequency | — | 420.17 MHz |
| Core Voltage | — | 1.5 V |
| Process Technology | — | 130 nm CMOS |
| Package Body Size | — | 35 mm x 35 mm |
| Ball Pitch | — | 1.27 mm |
| Lead-Free / RoHS | — | Yes (lead-free finish, RoHS compliant) |