EP1S20F672C7 vs EP1S20F672C7N 对比

详细并排对比 EP1S20F672C7 出自 Intel 和 EP1S20F672C7N 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

Intel
EP1S20F672C7 EP1S20F672C7 - Stratix FPGA 18,460 LEs 672-BGA | Intel

EP1S20F672C7 - Stratix FPGA 18,460 LEs 672-BGA | Intel

EP1S20F672C7 ⚠ 最后一次采购

规格对比

参数 EP1S20F672C7 EP1S20F672C7N
品牌 Intel Intel
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 最后采购期 Obsolete
库存状态 有库存 有库存
单价(USD) $195.00 $109.20
Series Stratix Stratix (first generation)
Family Altera Stratix FPGA Stratix
Logic Elements (LEs) 18,460 18,460
Embedded Memory Bits 1,669,248 —
User I/O Pins 426 —
DSP Blocks [DATA_NEEDED: DSP block count] 56 (dedicated 18x18 multipliers)
封装 672-ball FineLine BGA (35 x 35 mm, 1.27 mm pitch) 672-FBGA (FineLine BGA)
Logic Family CMOS, SRAM-based —
Core Supply Voltage 1.5 V —
工作温度 0C to 85C (commercial) 0°C to +85°C (commercial)
Speed Grade C7 C7 (-7)
Configuration Modes JTAG, Passive Serial, Fast Passive Parallel, Active Serial PS, PPS, FPP, JTAG
安装类型 Surface Mount Surface Mount
MSL 等级 [DATA_NEEDED: MSL level] [DATA_NEEDED: moisture sensitivity level]
RoHS 状态 unknown —
Clock PLLs Up to 10 —
Logic Cells — 18,460
Configurable Logic Blocks (CLBs) — 2,132
Embedded Memory (TriMatrix) — 1,669,248 bits (426 Kbit total)
Maximum User I/O — 586
I/O Banks — [DATA_NEEDED: I/O bank count]
PLLs — Up to 12
Maximum Operating Frequency — 420.17 MHz
Core Voltage — 1.5 V
Process Technology — 130 nm CMOS
Package Body Size — 35 mm x 35 mm
Ball Pitch — 1.27 mm
Lead-Free / RoHS — Yes (lead-free finish, RoHS compliant)

数据手册与资源

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