EP1S25F672C8 vs EP1S25F672C5N Comparación
Comparación detallada lado a lado de EP1S25F672C8 por Intel y EP1S25F672C5N por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP1S25F672C8 | EP1S25F672C5N |
|---|---|---|
| Marca | Intel | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $525,00 | $142,00 |
| Family | Stratix | Stratix |
| Logic Elements | 25,660 | — |
| Logic Array Blocks (LABs) | 2,566 | — |
| User I/Os | 473 | — |
| Process Technology | 130 nm CMOS | 130 nm CMOS |
| Core Supply Voltage | 1.5 V | 1.5 V (nominal) |
| Maximum Operating Frequency | 357.14 MHz | — |
| Encapsulado | 672-ball FineLine BGA (FBGA) | — |
| Package Dimensions | 35 x 35 mm, 1.27 mm pitch | — |
| Speed Grade | C8 (commercial, -8) | C5 |
| Temperatura de funcionamiento | 0 C to +85 C (commercial) | — |
| Tipo de montaje | Surface Mount | Surface Mount (BGA) |
| Nivel MSL | [DATA_NEEDED: MSL Level] | — |
| Estado RoHS | [DATA_NEEDED: RoHS Status] | Compliant |
| Logic Family | CMOS | — |
| Configuration Method | JTAG / Altera configuration device | SRAM-based, programmable via JTAG / Passive Serial / Fast Passive Parallel |
| Series | — | EP1S25 |
| Logic Elements (Cells) | — | 25,660 |
| Number of CLBs | — | 2,566 |
| Number of Logic Cells / Gates | — | [DATA_NEEDED: total system gates] |
| Maximum Internal Frequency | — | 500 MHz |
| Number of I/O Pins | — | 473 user I/O |
| Number of I/O Banks | — | [DATA_NEEDED: I/O bank count] |
| Package Type | — | FineLine BGA (FBGA) |
| Package Pin Count | — | 672 |
| Ball Pitch | — | 1.00 mm |
| Rango de temperatura de funcionamiento | — | 0 °C to +85 °C (commercial) |
| Lead-Free (Pb-Free) | — | Yes (suffix "N") |