EP1S40B956C6N vs EP1S40F1020C5GA Comparación
Comparación detallada lado a lado de EP1S40B956C6N por Intel y EP1S40F1020C5GA por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP1S40B956C6N | EP1S40F1020C5GA |
|---|---|---|
| Marca | Intel | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $1.050,00 | $171,00 |
| Series | Stratix | Stratix |
| Family | Altera Stratix (1st generation) | — |
| Process Technology | 0.13 µm CMOS | — |
| Logic Elements (LEs) | 41,250 | — |
| Logic Array Blocks (LABs) | 4,125 | — |
| Embedded Memory | 3,423,744 bits (~3.4 Mbit) | — |
| Maximum User I/O | 683 | — |
| Tensión de alimentación | 1.425 V to 1.575 V (1.5 V nominal) | — |
| Temperatura de funcionamiento | 0 °C to +85 °C (Commercial) | 0C to +85C (Commercial) |
| Encapsulado | 956-ball FineLine BGA (FCBGA) | 1020-BBGA (FineLine BGA) |
| Package Dimensions | 40 mm x 40 mm | — |
| Ball Pitch | 1.27 mm | — |
| Speed Grade | C6 (commercial, mid-speed) | C5 |
| Configuration Interface | JTAG (IEEE 1149.1), Passive Serial, Active Serial | — |
| Tipo de montaje | Surface Mount | Surface Mount |
| Nivel MSL | [DATA_NEEDED: MSL rating] | [DATA_NEEDED: MSL rating] |
| Estado RoHS | [DATA_NEEDED: RoHS compliance] | Unknown - non-GA suffix commercial part |
| Logic Elements (LE) | — | 41,250 |
| Total RAM Bits | — | 3,423,744 |
| User I/O Count | — | 773 |
| Process Node | — | 0.13 µm CMOS with 9-layer metal |
| Supply Voltage (Core) | — | [DATA_NEEDED: VCCINT value] |
| I/O Bank Count | — | [DATA_NEEDED: bank count] |
| DSP Blocks | — | Embedded multiplier blocks (count per Stratix datasheet family) |
| PLL Count | — | Up to 12 enhanced PLLs (per Stratix family) |
| High-Speed Transceivers | — | Up to 12 channels (per Stratix family, variant dependent) |
| Configuration Method | — | JTAG, Passive Serial, Altera EPC device |
| Lead-Free | — | Yes (per Altera/Intel policy at release) |