EP1S40B956C6N vs EP1S40F1020C5GA Comparaison
Comparaison détaillée côte à côte de EP1S40B956C6N par Intel et EP1S40F1020C5GA par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP1S40B956C6N | EP1S40F1020C5GA |
|---|---|---|
| Marque | Intel | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $1 050,00 | $171,00 |
| Series | Stratix | Stratix |
| Family | Altera Stratix (1st generation) | — |
| Process Technology | 0.13 µm CMOS | — |
| Logic Elements (LEs) | 41,250 | — |
| Logic Array Blocks (LABs) | 4,125 | — |
| Embedded Memory | 3,423,744 bits (~3.4 Mbit) | — |
| Maximum User I/O | 683 | — |
| Tension d'alimentation | 1.425 V to 1.575 V (1.5 V nominal) | — |
| Température de fonctionnement | 0 °C to +85 °C (Commercial) | 0C to +85C (Commercial) |
| Boîtier | 956-ball FineLine BGA (FCBGA) | 1020-BBGA (FineLine BGA) |
| Package Dimensions | 40 mm x 40 mm | — |
| Ball Pitch | 1.27 mm | — |
| Speed Grade | C6 (commercial, mid-speed) | C5 |
| Configuration Interface | JTAG (IEEE 1149.1), Passive Serial, Active Serial | — |
| Type de montage | Surface Mount | Surface Mount |
| Niveau MSL | [DATA_NEEDED: MSL rating] | [DATA_NEEDED: MSL rating] |
| Statut RoHS | [DATA_NEEDED: RoHS compliance] | Unknown - non-GA suffix commercial part |
| Logic Elements (LE) | — | 41,250 |
| Total RAM Bits | — | 3,423,744 |
| User I/O Count | — | 773 |
| Process Node | — | 0.13 µm CMOS with 9-layer metal |
| Supply Voltage (Core) | — | [DATA_NEEDED: VCCINT value] |
| I/O Bank Count | — | [DATA_NEEDED: bank count] |
| DSP Blocks | — | Embedded multiplier blocks (count per Stratix datasheet family) |
| PLL Count | — | Up to 12 enhanced PLLs (per Stratix family) |
| High-Speed Transceivers | — | Up to 12 channels (per Stratix family, variant dependent) |
| Configuration Method | — | JTAG, Passive Serial, Altera EPC device |
| Lead-Free | — | Yes (per Altera/Intel policy at release) |