EP1S40B956C6N vs EP1S40F1020C5GA 对比

详细并排对比 EP1S40B956C6N 出自 Intel 和 EP1S40F1020C5GA 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP1S40B956C6N EP1S40F1020C5GA
品牌 Intel Intel
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $1,050.00 $171.00
Series Stratix Stratix
Family Altera Stratix (1st generation) —
Process Technology 0.13 µm CMOS —
Logic Elements (LEs) 41,250 —
Logic Array Blocks (LABs) 4,125 —
Embedded Memory 3,423,744 bits (~3.4 Mbit) —
Maximum User I/O 683 —
电源电压 1.425 V to 1.575 V (1.5 V nominal) —
工作温度 0 °C to +85 °C (Commercial) 0C to +85C (Commercial)
封装 956-ball FineLine BGA (FCBGA) 1020-BBGA (FineLine BGA)
Package Dimensions 40 mm x 40 mm —
Ball Pitch 1.27 mm —
Speed Grade C6 (commercial, mid-speed) C5
Configuration Interface JTAG (IEEE 1149.1), Passive Serial, Active Serial —
安装类型 Surface Mount Surface Mount
MSL 等级 [DATA_NEEDED: MSL rating] [DATA_NEEDED: MSL rating]
RoHS 状态 [DATA_NEEDED: RoHS compliance] Unknown - non-GA suffix commercial part
Logic Elements (LE) — 41,250
Total RAM Bits — 3,423,744
User I/O Count — 773
Process Node — 0.13 µm CMOS with 9-layer metal
Supply Voltage (Core) — [DATA_NEEDED: VCCINT value]
I/O Bank Count — [DATA_NEEDED: bank count]
DSP Blocks — Embedded multiplier blocks (count per Stratix datasheet family)
PLL Count — Up to 12 enhanced PLLs (per Stratix family)
High-Speed Transceivers — Up to 12 channels (per Stratix family, variant dependent)
Configuration Method — JTAG, Passive Serial, Altera EPC device
Lead-Free — Yes (per Altera/Intel policy at release)

数据手册与资源

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