EP20K200BC484-1X vs EP20K200BC484-2X Comparación
Comparación detallada lado a lado de EP20K200BC484-1X por Altera y EP20K200BC484-2X por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Altera
EP20K200BC484-1X - APEX-20K 200K-Gate FPGA 382 I/O 484-BGA | Altera
EP20K200BC484-1X ObsoleteComparación de especificaciones
| Parámetro | EP20K200BC484-1X | EP20K200BC484-2X |
|---|---|---|
| Marca | Altera | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | NRND |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $75,10 | $95,00 |
| Product Family | APEX-20K | — |
| Series | EP20K200 | EP20K200 |
| Logic Elements / Cells | 8320 | — |
| Total RAM Bits | 106496 | — |
| Number of I/O | 382 | — |
| Number of Logic Gates | 200000 | — |
| Package Type | 484-BBGA (Fine-pitch Ball Grid Array) | — |
| Package Suffix | BC484 | — |
| Speed Grade | -1 (slowest commercial grade) | -2X |
| Tipo de montaje | Surface Mount | Surface Mount |
| Temperatura de funcionamiento | 0C to +85C (commercial, [DATA_NEEDED: full Tjj range]) | — |
| Configuration Method | SRAM - external serial/parallel PROM | — |
| JTAG Support | IEEE 1149.1 boundary-scan | — |
| PLL | ClockLock / ClockBoost | — |
| Embedded Memory Blocks | Embedded System Blocks (ESBs) - RAM/ROM/CAM | — |
| Nivel MSL | [DATA_NEEDED: MSL level] | — |
| Estado RoHS | [DATA_NEEDED: RoHS compliance] | Compliant (per supplier listings) |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Family | — | APEX-20K |
| Logic Elements | — | 8,320 |
| LABs/CLBs | — | 832 |
| Embedded RAM | — | 106,496 bits |
| User I/O Pins | — | 382 |
| Dedicated Inputs | — | 4 |
| Supply Voltage (VCCINT) | — | 2.375 V to 2.625 V |
| Temperatura de unión de funcionamiento | — | 0 °C to 85 °C |
| Encapsulado | — | 484-ball PBGA (BBGA-484) |
| Architecture | — | MultiCore™ (LUT + Embedded System Blocks) |
| Configuration | — | SRAM-based (requires external configuration memory) |
| Maximum Clock Frequency (reference) | — | 178.57 MHz (per Altera datasheet for family) |