EP20K200BC484-1X vs EP20K200BC484-2X 比較
詳細な並列比較: EP20K200BC484-1X メーカー: Altera および EP20K200BC484-2X メーカー: Intel。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
Altera
EP20K200BC484-1X - APEX-20K 200K-Gate FPGA 382 I/O 484-BGA | Altera
EP20K200BC484-1X Obsolete仕様比較
| パラメータ | EP20K200BC484-1X | EP20K200BC484-2X |
|---|---|---|
| ブランド | Altera | Intel |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | NRND |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $75.10 | $95.00 |
| Product Family | APEX-20K | — |
| Series | EP20K200 | EP20K200 |
| Logic Elements / Cells | 8320 | — |
| Total RAM Bits | 106496 | — |
| Number of I/O | 382 | — |
| Number of Logic Gates | 200000 | — |
| Package Type | 484-BBGA (Fine-pitch Ball Grid Array) | — |
| Package Suffix | BC484 | — |
| Speed Grade | -1 (slowest commercial grade) | -2X |
| 実装タイプ | Surface Mount | Surface Mount |
| 動作温度 | 0C to +85C (commercial, [DATA_NEEDED: full Tjj range]) | — |
| Configuration Method | SRAM - external serial/parallel PROM | — |
| JTAG Support | IEEE 1149.1 boundary-scan | — |
| PLL | ClockLock / ClockBoost | — |
| Embedded Memory Blocks | Embedded System Blocks (ESBs) - RAM/ROM/CAM | — |
| MSLレベル | [DATA_NEEDED: MSL level] | — |
| RoHS ステータス | [DATA_NEEDED: RoHS compliance] | Compliant (per supplier listings) |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Family | — | APEX-20K |
| Logic Elements | — | 8,320 |
| LABs/CLBs | — | 832 |
| Embedded RAM | — | 106,496 bits |
| User I/O Pins | — | 382 |
| Dedicated Inputs | — | 4 |
| Supply Voltage (VCCINT) | — | 2.375 V to 2.625 V |
| 動作接合温度 | — | 0 °C to 85 °C |
| パッケージ | — | 484-ball PBGA (BBGA-484) |
| Architecture | — | MultiCore™ (LUT + Embedded System Blocks) |
| Configuration | — | SRAM-based (requires external configuration memory) |
| Maximum Clock Frequency (reference) | — | 178.57 MHz (per Altera datasheet for family) |