EP20K200BC484-1X vs EP20K200BC484-2X Comparaison
Comparaison détaillée côte à côte de EP20K200BC484-1X par Altera et EP20K200BC484-2X par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Altera
EP20K200BC484-1X - APEX-20K 200K-Gate FPGA 382 I/O 484-BGA | Altera
EP20K200BC484-1X ObsoleteComparaison des spécifications
| Paramètre | EP20K200BC484-1X | EP20K200BC484-2X |
|---|---|---|
| Marque | Altera | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | NRND |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $75,10 | $95,00 |
| Product Family | APEX-20K | — |
| Series | EP20K200 | EP20K200 |
| Logic Elements / Cells | 8320 | — |
| Total RAM Bits | 106496 | — |
| Number of I/O | 382 | — |
| Number of Logic Gates | 200000 | — |
| Package Type | 484-BBGA (Fine-pitch Ball Grid Array) | — |
| Package Suffix | BC484 | — |
| Speed Grade | -1 (slowest commercial grade) | -2X |
| Type de montage | Surface Mount | Surface Mount |
| Température de fonctionnement | 0C to +85C (commercial, [DATA_NEEDED: full Tjj range]) | — |
| Configuration Method | SRAM - external serial/parallel PROM | — |
| JTAG Support | IEEE 1149.1 boundary-scan | — |
| PLL | ClockLock / ClockBoost | — |
| Embedded Memory Blocks | Embedded System Blocks (ESBs) - RAM/ROM/CAM | — |
| Niveau MSL | [DATA_NEEDED: MSL level] | — |
| Statut RoHS | [DATA_NEEDED: RoHS compliance] | Compliant (per supplier listings) |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Family | — | APEX-20K |
| Logic Elements | — | 8,320 |
| LABs/CLBs | — | 832 |
| Embedded RAM | — | 106,496 bits |
| User I/O Pins | — | 382 |
| Dedicated Inputs | — | 4 |
| Supply Voltage (VCCINT) | — | 2.375 V to 2.625 V |
| Température de jonction en fonctionnement | — | 0 °C to 85 °C |
| Boîtier | — | 484-ball PBGA (BBGA-484) |
| Architecture | — | MultiCore™ (LUT + Embedded System Blocks) |
| Configuration | — | SRAM-based (requires external configuration memory) |
| Maximum Clock Frequency (reference) | — | 178.57 MHz (per Altera datasheet for family) |