EP20K200EBC356-1 vs EP20K200BC356-1 Comparación
Comparación detallada lado a lado de EP20K200EBC356-1 por Altera y EP20K200BC356-1 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP20K200EBC356-1 | EP20K200BC356-1 |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $142,00 | $335,00 |
| Family | APEX 20K (APEX 20KE) | — |
| System Gates | 200,000 | — |
| Logic Elements / Cells | 8,320 | 8320 |
| Maximum User I/Os | 277 | — |
| Core Voltage | 1.8 V (1.71 V to 1.89 V) | — |
| Process Technology | 0.22 µm CMOS | 0.22 um |
| Propagation Delay | 2.5 ns | — |
| Internal Performance | Up to 367 MHz | — |
| Encapsulado | 356-ball LBGA (35 x 35 mm) | — |
| Tipo de montaje | Surface Mount (BGA) | Surface Mount |
| Temperatura de funcionamiento | 0 °C to 85 °C (Commercial) | — |
| Architecture | MultiCore (LUT + product-term + embedded memory) | — |
| On-chip Memory | Embedded System Blocks (ESB / SRAM) | — |
| Configuration Method | JTAG (ByteBlaster / MasterBlaster), passive serial | — |
| Development Software | Altera Quartus II | — |
| Estado RoHS | [DATA_NEEDED: RoHS status not stated in verified sources] | [DATA_NEEDED: RoHS/lead finish of original non-N EP20K200BC356-1] |
| Estado del ciclo de vida | Obsolete / EOL | — |
| Product Function | — | APEX-20K Field Programmable Gate Array (FPGA) |
| Logic Family | — | CMOS |
| Equivalent System Gates | — | 200K gates |
| Total RAM Bits | — | 106496 bits |
| Frecuencia de reloj máxima | — | 250 MHz |
| Core Supply Voltage | — | 2.5 V |
| User I/O Count | — | 277 |
| Número de pines | — | 356 |
| Encapsulado / Carcasa | — | 356-LBGA |
| Package Code | — | LBGA |
| Package Shape | — | Square |
| Propagation Delay (tPD) | — | 2.5 ns (from -1N variant listing) |
| Rango de temperatura de funcionamiento | — | 0 to 85 C (commercial, per -1N variant listing) |
| Lead-Free Finish | — | [DATA_NEEDED: original non-N finish not specified; N suffix indicates lead-free] |