EP20K200EBC356-1 vs EP20K200BC356-1 比較
詳細な並列比較: EP20K200EBC356-1 メーカー: Altera および EP20K200BC356-1 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EP20K200EBC356-1 | EP20K200BC356-1 |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $142.00 | $335.00 |
| Family | APEX 20K (APEX 20KE) | — |
| System Gates | 200,000 | — |
| Logic Elements / Cells | 8,320 | 8320 |
| Maximum User I/Os | 277 | — |
| Core Voltage | 1.8 V (1.71 V to 1.89 V) | — |
| Process Technology | 0.22 µm CMOS | 0.22 um |
| Propagation Delay | 2.5 ns | — |
| Internal Performance | Up to 367 MHz | — |
| パッケージ | 356-ball LBGA (35 x 35 mm) | — |
| 実装タイプ | Surface Mount (BGA) | Surface Mount |
| 動作温度 | 0 °C to 85 °C (Commercial) | — |
| Architecture | MultiCore (LUT + product-term + embedded memory) | — |
| On-chip Memory | Embedded System Blocks (ESB / SRAM) | — |
| Configuration Method | JTAG (ByteBlaster / MasterBlaster), passive serial | — |
| Development Software | Altera Quartus II | — |
| RoHS ステータス | [DATA_NEEDED: RoHS status not stated in verified sources] | [DATA_NEEDED: RoHS/lead finish of original non-N EP20K200BC356-1] |
| ライフサイクル状態 | Obsolete / EOL | — |
| Product Function | — | APEX-20K Field Programmable Gate Array (FPGA) |
| Logic Family | — | CMOS |
| Equivalent System Gates | — | 200K gates |
| Total RAM Bits | — | 106496 bits |
| 最大クロック周波数 | — | 250 MHz |
| Core Supply Voltage | — | 2.5 V |
| User I/O Count | — | 277 |
| ピン数 | — | 356 |
| パッケージ / ケース | — | 356-LBGA |
| Package Code | — | LBGA |
| Package Shape | — | Square |
| Propagation Delay (tPD) | — | 2.5 ns (from -1N variant listing) |
| 動作温度範囲 | — | 0 to 85 C (commercial, per -1N variant listing) |
| Lead-Free Finish | — | [DATA_NEEDED: original non-N finish not specified; N suffix indicates lead-free] |