EP20K400FI672-1XN vs EP20K400EFC672-1XN Comparación
Comparación detallada lado a lado de EP20K400FI672-1XN por Intel y EP20K400EFC672-1XN por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP20K400FI672-1XN | EP20K400EFC672-1XN |
|---|---|---|
| Marca | Intel | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | NRND | NRND |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $171,00 | $215,00 |
| Family | APEX 20K | APEX 20K |
| Device | EP20K400 | — |
| Typical Gates | 400,000 | — |
| Logic Elements | 16,640 | — |
| Maximum User I/O Pins | 488 | — |
| Embedded System Memory | 212 Kbit | — |
| Number of PLLs | 4 | — |
| Core Supply Voltage | 2.5 V (2.375 V to 2.625 V) | — |
| I/O Supply Voltage | 2.5 V / 3.3 V | — |
| Process Technology | 0.18 micrometer CMOS | 0.18 µm CMOS |
| Encapsulado | 672-ball FineLine BGA (FI672) | 672-BBGA (FC-FBGA, FineLine BGA) |
| Package Size | 27 mm x 27 mm | — |
| Temperatura de funcionamiento | -40 C to +85 C (industrial) | — |
| Configuration Method | SRAM, JTAG, EPC serial PROM | — |
| JTAG Support | IEEE 1149.1 boundary-scan compliant | — |
| Speed Grade | -1 | — |
| Estado RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Nivel MSL | 3 | — |
| Series | — | APEX-20KE |
| Logic Elements / Cells | — | 16,640 |
| Logic Array Blocks (LABs) | — | 1,664 |
| System Gates | — | 400,000 |
| Total RAM Bits | — | 212,992 |
| User I/O | — | 488 |
| Number of I/O Banks | — | [DATA_NEEDED: I/O bank count] |
| Supply Voltage - Core | — | 1.8 V |
| I/O Voltage Standards | — | 1.5 V / 1.8 V / 2.5 V / 3.3 V (MultiVolt) |
| Embedded PLLs | — | 4 |
| Maximum Internal Frequency | — | [DATA_NEEDED: max internal frequency] |
| Tipo de montaje | — | Surface Mount |
| Operating Temperature Grade | — | Industrial / Other (per MPN suffix) |
| Configuration Mode | — | Passive Serial / Passive Parallel / JTAG (IEEE 1149.1) |