EP20K400FI672-3 vs EP20K400FI672-1 Comparación
Comparación detallada lado a lado de EP20K400FI672-3 por Altera y EP20K400FI672-1 por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP20K400FI672-3 | EP20K400FI672-1 |
|---|---|---|
| Marca | Altera | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $195,00 | $92,00 |
| Family | APEX 20K | — |
| Series | EP20K400 | APEX 20K |
| Logic Elements | 16640 | 212,992 |
| Total Gates | up to 400000 | — |
| Embedded RAM | 212992 bits | — |
| Maximum User I/O | 502 | — |
| Dedicated Inputs | 6 | 4 |
| Propagation Delay | 3.6 ns | 2.5 ns |
| Frecuencia de reloj máxima | 833 MHz | — |
| Supply Voltage (Nominal) | 2.5 V | — |
| Supply Voltage Range | 2.375 V to 2.625 V | — |
| Process Technology | CMOS | CMOS |
| Package Type | PBGA (Plastic BGA) | — |
| Package Code | S-PBGA-B672 | — |
| Terminal Count | 672 | — |
| Terminal Pitch | 1.000 mm | — |
| Package Shape | Square BGA | — |
| Tipo de montaje | Surface Mount | — |
| Configuration Interface | JTAG (IEEE 1149.1) | — |
| Temperatura de funcionamiento | [DATA_NEEDED: operating temperature range] | Industrial (per 'I' suffix) |
| Nivel MSL | 3 | 3 |
| Peak Reflow Temperature | 220 C | 220 C |
| Device Family | — | APEX-20K Field Programmable Gate Array |
| Typical Gates | — | 400,000 |
| Logic Array Blocks (LABs) | — | 16,640 |
| User I/O Pins | — | 502 |
| Total Terminals | — | 672 |
| Encapsulado | — | 672-ball PBGA (FineLine BGA, 1.0 mm pitch) |
| Package Code (JEDEC) | — | S-PBGA-B672 |
| Core Supply Voltage (VCCINT) | — | 2.5 V nominal (2.375 V to 2.625 V) |
| Speed Grade | — | -1 |
| Estado RoHS | — | [DATA_NEEDED: RoHS compliance] |