EP20K600CF672C-9 vs EP20K600CF672C6 Comparación
Comparación detallada lado a lado de EP20K600CF672C-9 por Altera y EP20K600CF672C6 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Altera
EP20K600CF672C-9 - 600K Gates APEX 20KC FPGA 488 I/O BGA-672 | Altera
EP20K600CF672C-9 Obsolete
Comparación de especificaciones
| Parámetro | EP20K600CF672C-9 | EP20K600CF672C6 |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $171,00 | $480,00 |
| Device Type | FPGA (APEX 20KC family, complex PLD) | — |
| Typical Gate Count | 600,000 gates | 600,000 gates |
| Logic Elements (LEs) | [DATA_NEEDED: logic element count] | 24,320 |
| Embedded System Blocks (ESBs) | [DATA_NEEDED: ESB count and total RAM bits] | 160 (each 2,048 bits) |
| User I/Os | 488 pins | — |
| PLLs | 4 | — |
| Encapsulado | 672-ball FBGA (45 x 45 mm, 1.27 mm pitch) | 672-ball FineLine BGA (CF672) |
| Recuento de pines | 672 | — |
| Core Supply Voltage (VCCINT) | 1.8 V | — |
| I/O Supply Voltage (VCCIO) | 1.8 V / 2.5 V / 3.3 V / 5.0 V (MultiVolt I/O) | — |
| Propagation Delay | 1.48 ns | — |
| Temperatura de funcionamiento | 0 °C to +85 °C (commercial) | 0 °C to +85 °C (commercial) |
| Speed Grade | -9 | -6 (C6) |
| Process Technology | 0.15 µm all-layer copper interconnect | 0.18 µm CMOS, 6 metal layers |
| Configuration Interface | Serial (EPC16 / EPC8 / EPC4 / EPC2 / EPC1) | — |
| Tipo de montaje | Surface Mount (BGA) | — |
| Estado RoHS | unknown | Non-RoHS (legacy process) |
| Family | — | APEX 20KC |
| Maximum Embedded RAM | — | 311,296 bits (311 kbit) |
| Maximum User I/O Pins | — | 508 |
| Package Body Size | — | 27 mm × 27 mm |
| Core Voltage | — | 1.8 V |
| I/O Standards Supported | — | LVCMOS, LVTTL, HSTL, SSTL, GTL+ |
| Embedded PLLs | — | 4 |
| Configuration Method | — | SRAM-based, JTAG, EPC16/EPC2 |