EP20K600CF672I9N vs EP20K600CF672I7N Comparación
Comparación detallada lado a lado de EP20K600CF672I9N por Intel y EP20K600CF672I7N por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP20K600CF672I9N | EP20K600CF672I7N |
|---|---|---|
| Marca | Intel | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | NRND | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $120,00 | $232,00 |
| Family | APEX 20KC | APEX 20KC |
| Logic Elements | 24,320 cells | 24,320 |
| Typical Gates | 600,000 | — |
| Maximum Frequency | 250 MHz | — |
| Process Technology | 0.15 µm CMOS | — |
| Core Voltage (VCCINT) | 1.8 V | 1.8 V |
| I/O Voltage (VCCIO) | [DATA_NEEDED: VCCIO range] | 2.5 V / 3.3 V (MultiVolt, bank-dependent) |
| Embedded Memory | 311,040 bits (approx. 38 KB) | — |
| Encapsulado | 672-ball FC-FBGA | 672-ball FineLine BGA (FC-FBGA) |
| PLL Count | [DATA_NEEDED: PLL count] | — |
| User I/O Pins | [DATA_NEEDED: max user I/O] | — |
| Configuration Mode | JTAG / Serial / Parallel | — |
| Programming Interface | IEEE 1149.1 JTAG | — |
| Temperatura de funcionamiento | -40 °C to +85 °C (industrial) | — |
| Estado RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance] |
| Technology | — | 0.15 µm CMOS |
| Maximum System Gates | — | 600,000 |
| Maximum User I/O Pins | — | 508 |
| Maximum Internal Frequency | — | 376 MHz |
| Embedded System Blocks (ESBs) | — | 160 |
| Total Embedded RAM (max) | — | 311,296 bits |
| Ball Pitch | — | 1.0 mm |
| Package Body Size | — | 27 mm × 27 mm |
| Speed Grade | — | I7 (-40 °C to +100 °C industrial) |
| Propagation Delay (typical) | — | 1.6 ns |
| Configuration Method | — | JTAG (IEEE 1149.1) + EPC configuration device |
| Lead-Free Finish (N suffix) | — | Yes |