EP20K600CF672I9N vs EP20K600CF672I7N Comparaison
Comparaison détaillée côte à côte de EP20K600CF672I9N par Intel et EP20K600CF672I7N par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP20K600CF672I9N | EP20K600CF672I7N |
|---|---|---|
| Marque | Intel | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | NRND | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $120,00 | $232,00 |
| Family | APEX 20KC | APEX 20KC |
| Logic Elements | 24,320 cells | 24,320 |
| Typical Gates | 600,000 | — |
| Maximum Frequency | 250 MHz | — |
| Process Technology | 0.15 µm CMOS | — |
| Core Voltage (VCCINT) | 1.8 V | 1.8 V |
| I/O Voltage (VCCIO) | [DATA_NEEDED: VCCIO range] | 2.5 V / 3.3 V (MultiVolt, bank-dependent) |
| Embedded Memory | 311,040 bits (approx. 38 KB) | — |
| Boîtier | 672-ball FC-FBGA | 672-ball FineLine BGA (FC-FBGA) |
| PLL Count | [DATA_NEEDED: PLL count] | — |
| User I/O Pins | [DATA_NEEDED: max user I/O] | — |
| Configuration Mode | JTAG / Serial / Parallel | — |
| Programming Interface | IEEE 1149.1 JTAG | — |
| Température de fonctionnement | -40 °C to +85 °C (industrial) | — |
| Statut RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance] |
| Technology | — | 0.15 µm CMOS |
| Maximum System Gates | — | 600,000 |
| Maximum User I/O Pins | — | 508 |
| Maximum Internal Frequency | — | 376 MHz |
| Embedded System Blocks (ESBs) | — | 160 |
| Total Embedded RAM (max) | — | 311,296 bits |
| Ball Pitch | — | 1.0 mm |
| Package Body Size | — | 27 mm × 27 mm |
| Speed Grade | — | I7 (-40 °C to +100 °C industrial) |
| Propagation Delay (typical) | — | 1.6 ns |
| Configuration Method | — | JTAG (IEEE 1149.1) + EPC configuration device |
| Lead-Free Finish (N suffix) | — | Yes |