EP2A15B724C8 vs EP2A15B724C Comparación
Comparación detallada lado a lado de EP2A15B724C8 por Intel y EP2A15B724C por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP2A15B724C8 | EP2A15B724C |
|---|---|---|
| Marca | Intel | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | NRND | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $185,00 | $195,00 |
| Family | APEX II | APEX II |
| Manufacturer | Intel (formerly Altera) | — |
| Logic Elements | 16,640 | — |
| System Gates | 600,000 | — |
| Embedded RAM Bits | 425,984 | — |
| User I/O | 492 | — |
| Maximum Internal Frequency | 435 MHz | — |
| Pin-to-Pin Logic Delay (tPD) | 1.94 ns | — |
| Core Voltage | 1.5 V | — |
| Process Technology | 0.15 µm all-layer copper, up to 8 metal layers | 0.18 micron CMOS |
| High-Speed Serial Support | 1 Gbps True-LVDS, LVPECL, PCML, HyperTransport | — |
| PLLs | 4 | Yes (family-level, up to 4 per device) |
| Encapsulado | 724-pin FCBGA (flip-chip BGA) | 724-Ball FCBGA (FineLine BGA) |
| Tipo de montaje | Surface Mount | Surface Mount (BGA) |
| Estado RoHS | unknown | [DATA_NEEDED: RoHS compliance] |
| Nivel MSL | [DATA_NEEDED: MSL level] | [DATA_NEEDED: MSL rating] |
| Rango de temperatura de funcionamiento | [DATA_NEEDED: operating temperature grade] | — |
| Logic Elements (LEs) | — | 16,640 |
| Maximum User I/O Pins | — | 492 |
| Embedded RAM | — | 425,984 bits |
| Maximum System Gates | — | Up to 1.5M gates (family-level) |
| Embedded System Blocks (ESBs) | — | Configurable as dual-port RAM / ROM / FIFO |
| Interconnect | — | MultiTrack, deterministic |
| I/O Standards | — | LVTTL, LVCMOS, LVDS, PCI, GTL+ (family-level) |
| Temperatura de funcionamiento | — | [DATA_NEEDED: operating temperature grade] |
| Speed Grade | — | C (per suffix; specific speed bin [DATA_NEEDED]) |
| JTAG / Configuration | — | IEEE 1149.1 JTAG; passive serial / PS configuration supported (family-level) |