EP2A15B724C8 vs EP2A15B724C Comparaison
Comparaison détaillée côte à côte de EP2A15B724C8 par Intel et EP2A15B724C par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP2A15B724C8 | EP2A15B724C |
|---|---|---|
| Marque | Intel | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | NRND | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $185,00 | $195,00 |
| Family | APEX II | APEX II |
| Manufacturer | Intel (formerly Altera) | — |
| Logic Elements | 16,640 | — |
| System Gates | 600,000 | — |
| Embedded RAM Bits | 425,984 | — |
| User I/O | 492 | — |
| Maximum Internal Frequency | 435 MHz | — |
| Pin-to-Pin Logic Delay (tPD) | 1.94 ns | — |
| Core Voltage | 1.5 V | — |
| Process Technology | 0.15 µm all-layer copper, up to 8 metal layers | 0.18 micron CMOS |
| High-Speed Serial Support | 1 Gbps True-LVDS, LVPECL, PCML, HyperTransport | — |
| PLLs | 4 | Yes (family-level, up to 4 per device) |
| Boîtier | 724-pin FCBGA (flip-chip BGA) | 724-Ball FCBGA (FineLine BGA) |
| Type de montage | Surface Mount | Surface Mount (BGA) |
| Statut RoHS | unknown | [DATA_NEEDED: RoHS compliance] |
| Niveau MSL | [DATA_NEEDED: MSL level] | [DATA_NEEDED: MSL rating] |
| Plage de température de fonctionnement | [DATA_NEEDED: operating temperature grade] | — |
| Logic Elements (LEs) | — | 16,640 |
| Maximum User I/O Pins | — | 492 |
| Embedded RAM | — | 425,984 bits |
| Maximum System Gates | — | Up to 1.5M gates (family-level) |
| Embedded System Blocks (ESBs) | — | Configurable as dual-port RAM / ROM / FIFO |
| Interconnect | — | MultiTrack, deterministic |
| I/O Standards | — | LVTTL, LVCMOS, LVDS, PCI, GTL+ (family-level) |
| Température de fonctionnement | — | [DATA_NEEDED: operating temperature grade] |
| Speed Grade | — | C (per suffix; specific speed bin [DATA_NEEDED]) |
| JTAG / Configuration | — | IEEE 1149.1 JTAG; passive serial / PS configuration supported (family-level) |