EP2A25F672C7 vs EP2A25F672I-9 Comparación
Comparación detallada lado a lado de EP2A25F672C7 por Altera y EP2A25F672I-9 por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP2A25F672C7 | EP2A25F672I-9 |
|---|---|---|
| Marca | Altera | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | NRND | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $118,00 | $195,00 |
| Product Family | APEX II | — |
| Logic Elements | 25,000 | — |
| Maximum System Gates | 1,650,000 | [DATA_NEEDED: maximum system gates] |
| Maximum RAM Bits | 422,976 | — |
| User I/O Count | 492 | — |
| Encapsulado | 672-ball FCBGA (FineLine BGA) | 672-pin FCBGA (FineLine BGA) |
| Process Technology | 0.15-um all-layer copper, up to 8 metal layers | 0.18 µm CMOS |
| Supply Voltage (Core) | 1.5 V | — |
| LVDS Data Rate | 1 Gbps per channel (True-LVDS) | — |
| I/O Standards Supported | LVDS, LVPECL, PCML, HyperTransport | — |
| Temperatura de funcionamiento | 0C to +85C (Commercial) | — |
| Speed Grade | -7 | -9 |
| Configuration Mode | Passive Serial, Passive Parallel, JTAG | — |
| Estado RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Embedded System Blocks (ESB) | Yes - RAM, ROM, CAM, multiplier support | — |
| Family | — | APEX II |
| Logic Elements (typical) | — | 25,000 |
| Embedded System Blocks (ESB) Memory | — | 1,125 Kbits |
| Maximum User I/O Pins | — | [DATA_NEEDED: maximum user I/O pins] |
| Number of PLLs | — | 4 |
| Core Voltage | — | 1.5 V / 1.8 V (speed-grade dependent) |
| Operating Temperature Grade | — | Industrial (-40 °C to +100 °C junction) |
| Tipo de montaje | — | Surface Mount (BGA) |
| Nivel de sensibilidad a la humedad (MSL) | — | 3 (per Vyrian listing) |
| Peak Reflow Temperature | — | 220 °C (per Vyrian listing) |
| Configuration Method | — | JTAG / serial configuration EPROM |
| Supported I/O Standards | — | LVTTL, LVCMOS, LVDS, PCI |
| Legacy Status | — | Obsolete - consult Altera / Intel FPGA archive for documentation |